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19-4252; Rev 1; 10/08
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
General Description
The MAX1329/MAX1330 are smart data acquisition systems (DASs) based on a successive approximation register (SAR) analog-to-digital converter (ADC). These devices are highly integrated, offering an ADC, digitalto-analog converters (DACs), operational amplifiers (op amps), voltage reference, temperature sensors, and analog switches in the same device. The MAX1329/MAX1330 offer a single ADC with a reference buffer. The ADC is capable of operating in one of two user-programmable modes. In normal mode, the ADC provides up to 12 bits of resolution at 312ksps. In DSP mode, the ADC provides up to 16 bits of resolution at 1000sps. The ADC accepts one external differential input or two external single-ended inputs as well as inputs from other circuitry on-board. An on-chip programmable gain amplifier (PGA) follows the analog inputs, reducing external circuitry requirements. The PGA gain is adjustable from 1V/V to 8V/V. The MAX1329/MAX1330 operate from a 1.8V to 3.6V digital power supply. Shutdown and sleep modes are available for power-saving applications. Under normal operation, an internal charge pump boosts the supply voltage for the analog circuitry when the supply is < 2.7V. The MAX1329/MAX1330 offer four analog programmable I/Os (APIOs) and four digital programmable I/Os (DPIOs). The APIOs can be configured as general-purpose logic inputs and outputs, as a wake-up function, or as a buffer and level shifter for the serial interface to communicate with slave devices powered by the analog supply, AVDD. The DPIOs can be configured as generalpurpose logic inputs and outputs as well as inputs to directly control the ADC conversion rate, the analog switches, the loading of the DACs, wake-up, sleep, and shutdown modes, and as an interrupt for when the analog-to-digital conversion is complete. The MAX1329 includes dual 12-bit force-sense DACs with a programmable reference buffer and one op amp. The MAX1330 provides one 12-bit force-sense DAC with a programmable reference buffer and two op amps. For the MAX1329/MAX1330, a 16-word DAC FIFO can be used with the DACA for direct digital synthesis (DDS) of waveforms. The 4-wire serial interface is compatible with SPITM, QSPITM, and MICROWIRETM.
Features
1.8V to 3.6V Single Digital Supply Operation Internal Charge Pump for Analog Circuits (2.7V to 5.5V) 12-Bit SAR ADC 12 Bits, 312ksps, No Missing Codes 16 Bits, 1000sps, DSP Mode 16-Word FIFO and 20-Bit Accumulator PGA with Gains of 1, 2, 4, and 8 Unipolar and Bipolar Modes 16-Input Differential Multiplexer Dual 12-Bit Force-Sense DACs 16-Word FIFO (DACA Only) Independent Voltage References for ADC and DACs Internal 2.5V Reference Adjustable Reference Buffers Provide 1.25V, 2.048V, or 2.5V System Support ADC Alarm Register Uncommitted Op Amps Dual SPDT Analog Switches Internal/External Temperature Sensor Internal Oscillator with Clock I/O Digital Programmable I/O Analog Programmable I/O Programmable Interrupts Accurate Supply Voltage Measurement Programmable Dual Voltage Monitors SPI-/QSPI-/MICROWIRE-Compatible, 4-Wire Serial Interface Space-Saving, 6mm x 6mm, 40-Pin Thin QFN Package
MAX1329/MAX1330
Ordering Information
PART MAX1329BETL+ MAX1330BETL+* TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 40 Thin QFN-EP** 40 Thin QFN-EP**
Applications
Battery-Powered and Portable Devices Electrochemical and Optical Sensors Medical Instruments Industrial Control Data Acquisition Systems Low-Cost CODECs
SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
*Future product--contact factory for availability. **EP = Exposed pad. +Denotes a lead-free/RoHS-compliant package.
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V Analog Inputs to AGND....................................-0.3V to the lower of (AVDD + 0.3V) or +6V Digital Inputs to DGND.....................................-0.3V to the lower of (DVDD + 0.3V) or +6V Analog Outputs to AGND .................................-0.3V to the lower of (AVDD + 0.3V) or +6V Digital Outputs to DGND ..................................-0.3V to the lower of (DVDD + 0.3V) or 6V AGND to DGND.................................................... -0.3V to +0.3V Continuous Current into Any Pin.......................................50mA Continuous Power Dissipation (TA = +70C) 40-Pin Thin QFN (derate 37mW/C above +70C) ....2963mW Operation Temperature Range............................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DVDD = 1.8V to 3.6V, AVDD = 2.7V to 5.5V, VREFDAC = VREFADC = 2.5V, external reference; 10F capacitor at REFADC and REFDAC; 0.01F capacitor at REFADJ; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER ADC Resolution DSP-Mode Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Drift Gain = 1 Gain Error (Excluding Reference) (Note 1) Gain Temperature Coefficient Gain = 2, 4 Gain = 8 Excluding reference Unipolar mode, gain = 1, 2, 4, 8 Voltage Range Bipolar mode, gain = 1, 2, 4, 8 Absolute Input Voltage Range Input Leakage Current into Analog Inputs Input Capacitance Acquisition Time Conversion Time Conversion Clock Frequency Normal operation mode, ADC converting at 234ksps ADC Supply Current (Note 3) Fast power-down mode, ADC converting at 234ksps tAD tACQ tCONV (Note 2) Gain = 1, 2 Gain = 4, 8 Gain = 1, 2 Gain = 4, 8 12 clocks 0.6 1.2 2.4 0.1 325 A 210 30 ns 5.0 0 -VREFADC/ (2 x Gain) AGND 0.5 24 48 0.8 +VREFADC/ Gain +VREFADC/ (2 x Gain) AVDD 1 V INL DNL No missing codes 256 oversampling, dither enabled Normal mode (Note 1) Normal mode (Note 1) (Note 1) 1.5 0.1 1.5 2.5 ppm/C % FS 12 16 1 1 4 Bits Bits LSB12 LSB12 mV V/C SYMBOL CONDITIONS MIN TYP MAX UNITS
V nA pF s s MHz
Aperture Delay
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = 1.8V to 3.6V, AVDD = 2.7V to 5.5V, VREFDAC = VREFADC = 2.5V, external reference; 10F capacitor at REFADC and REFDAC; 0.01F capacitor at REFADJ; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Aperture Jitter SYMBOL tAJ Gain = 1, 2; DVDD 2.7V, AVDD 5.0V Sample Rate Gain = 4, 8; DVDD 2.7V, AVDD 5.0V Gain = 1, 2 Gain = 4, 8 Power-Supply Rejection Turn-On Time Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Full-Power Bandwidth Resolution Differential Nonlinearity Integral Nonlinearity Offset Error Offset-Error Temperature Coefficient Gain Error Gain-Error Temperature Coefficient Output Voltage Range Output Slew Rate Output Settling Time FB_ Input Bias Current FB_ Switch Resistance FB_ Switch Turn-On/-Off Time FB_ Switch Off Isolation FB_ Switch Charge Injection DAC-to-DAC Crosstalk Short-Circuit Current DC Output Impedance Power-Up Time Power-Supply Rejection Charge-Pump Output Feedthrough PSR Sink Source Code = 0x800 0.5 LSB settling to 0x800 AVDD = 2.7V to 5.5V Code = 0x800, buffer on, RL = 5k, CL = 200pF f = 10kHz 40 100 1 0.5 13 50 0.8 5 1 100 DNL INL Guaranteed monotonic (Note 4) (Note 4) Code = 0x000 (tested at 0x032) Due to amplifier Code = 0xFFF Excluding reference drift No load CL = 200pF Code = 0x400 to 0xC00 (Note 2) (Note 2) AGND 0.5 4 0.1 10 1 200 1 2.5 7 0 7 AVDD 5 FPBW -3dB point 12 1.0 8 30 DAC (RL = 5k, CL = 200pF, tested in unity gain, unless otherwise noted) Bits LSB LSB mV V/C % FS ppm/C V V/s s nA ns dB pC nV-s mA s mV/V VRMS SINAD THD SFDR Up to the 5th harmonic PSR AVDD = 2.7V to 5.5V, full-scale input Supply and reference have settled 0.06 1 71 82 84 100 4 CONDITIONS MIN TYP 50 312 263 234 200 0.5 mV/V s dB dB dB dB MHz ksps MAX UNITS ps
MAX1329/MAX1330
ADC DYNAMIC ACCURACY (10kHz sine wave, VIN = 2.5VP-P, fSAMPLE = 234ksps, gain = 1)
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = 1.8V to 3.6V, AVDD = 2.7V to 5.5V, VREFDAC = VREFADC = 2.5V, external reference; 10F capacitor at REFADC and REFDAC; 0.01F capacitor at REFADJ; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Power-Down Output Leakage Current Supply Current per DAC No load (Note 3) TA = +25C, AREF<1:0> = DREF<1:0> = 01 TA = +25C, AREF<1:0> = DREF<1:0> = 10 TA = +25C, AREF<1:0> = DREF<1:0> = 11 Output-Voltage Temperature REFADC and REFDAC Output Short-Circuit Current REFADC and REFDAC Line Regulation Load Regulation Long-Term Stability Turn-On Time Turn-Off Time Internal reference Reference Supply Current (Note 3) EXTERNAL REFERENCE AT REFADJ AREF<1:0> = DREF<1:0> = 11 External Reference Input Voltage Range AREF<1:0> = DREF<1:0> = 10 AREF<1:0> = DREF<1:0> = 01 Input Resistance AREF<1:0> = 01 REFADC Buffer Gain AREF<1:0> = 10 AREF<1:0> = 11 DREF<1:0> = 01 REFDAC Buffer Gain Minimum Capacitive Bypass DREF<1:0> = 10 DREF<1:0> = 11 REFADJ to AGND 50 1.225V 1.496V to AVDD - 0.1V 2.450V to AVDD - 0.1V 75 1 0.8192 0.5 1 0.8192 0.5 10 nF V/V V/V k AVDD - 0.1V V REFADC buffer REFDAC buffer ISOURCE = 0A to 500A, TA = +25C ISINK = 0A to 80A, TA = +25C TA = +25C At REFADJ 100 2 100 445 270 270 A (Note 2) Source Sink 1.225 2.007 2.450 70 1.250 2.048 2.500 10 40 13 100 600 10 10 1.275 2.089 2.550 75 ppm/C mA V/V V/A ppm/ 1000hrs ms ns V INTERNAL REFERENCE (10F capacitor at REFADC and REFDAC, 0.01F capacitor at REFADJ) Output Voltage at REFADC and REFDAC SYMBOL CONDITIONS MIN TYP MAX 100 UNITS nA A
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = 1.8V to 3.6V, AVDD = 2.7V to 5.5V, VREFDAC = VREFADC = 2.5V, external reference; 10F capacitor at REFADC and REFDAC; 0.01F capacitor at REFADJ; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER External Reference Input Voltage Range REFADC Input Resistance REFADC Input Current Turn-On Time Shutdown REFADC Input Current Minimum Capacitive Bypass EXTERNAL REFERENCE AT REFDAC REFDAC Input Voltage Range REFDAC Input Resistance REFDAC Input Current Turn-On Time Shutdown REFDAC Input Current Minimum Capacitive Bypass MULTIPLEXER Absolute Input Voltage Range Absolute Input Leakage Current Input Capacitance On Resistance INTERNAL TEMPERATURE SENSOR Internal Sensor Measurement Error (Note 5) External Sensor Measurement Error (Note 5) TA = +25C TA = -40C to +85C TA = +25C TA = 0C to +70C TA = -40C to +85C 0.4 2 3 C 0.25 3 C (AGND + 100mV) < VAIN_ < (AVDD - 100mV) (Note 2) ADC gain = 1, 2 ADC gain = 4, 8 AGND 0.01 24 48 340 AVDD 1 V nA pF REFDAC to AGND 10 MAX1329 MAX1330 MAX1329, VREFDAC = 2.5V MAX1330, VREFDAC = 2.5V REFDAC buffer AGND 64 128 90 180 28 14 75 0.1 1 AVDD 180 360 86 43 V k A s A F REFADC to AGND 10 VREFADC = 2.5V, 300ksps REFADC buffer, CREFADC = 1F SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1329/MAX1330
EXTERNAL REFERENCE AT REFADC AGND 50 75 30 75 0.01 1.0 40 AVDD V k A s A F
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = 1.8V to 3.6V, AVDD = 2.7V to 5.5V, VREFDAC = VREFADC = 2.5V, external reference; 10F capacitor at REFADC and REFDAC; 0.01F capacitor at REFADJ; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Temperature Resolution External-Diode Drive Ratio Temperature-Sensor Supply Current Temperature-Sensor Conversion Time CHARGE PUMP Input Voltage No-Load Output Voltage Output Current No-Load Supply Current Switching Frequency Switch Turn-On/-Off Time Switch Impedance Efficiency DVDD VOLTAGE MONITOR (VM1) Supply Voltage Range Trip Threshold (DVDD Falling) Hysteresis Reset Timeout Period Turn-On Time AVDD VOLTAGE MONITOR (VM2) Supply Voltage Range VM2CP<1:0> = 01 Trip Threshold (AVDD Falling) (Note 6) VATH VM2CP<1:0> = 10 VM2CP<1:0> = 11 VM2CP<1:0> = 01 Hysteresis VAHYS VM2CP<1:0> = 10 VM2CP<1:0> = 11 1.0 2.53 3.4 4.25 2.775 3.700 4.625 22.5 30 37.5 mV 5.5 2.975 3.925 4.925 V V VDTH VDHYS VM1<1:0> = 0x, RST1 input VM1<1:0> = x0, RST2 input VM1<1:0> = 0x, RST1 input VM1<1:0> = x0, RST2 input VDVDD = VDTH + VDHYS DVDD = 1.8V, enabled by VM1 <1:0> 1.0 1.80 2.65 1.865 2.750 15 22.5 170 2 3.6 1.93 2.90 V V mV ms ms Between DVDD to AVDD, charge pump off Shorts DVDD to AVDD, charge pump off 25mA load, DVDD = 1.8V, AVDD = 3.0V, 39kHz clock DVDD DVDD = 1.8V to 3.0V, VM2CP<2:0> = 001 AVDD DVDD = 2.2V to 3.6V, VM2CP<2:0> = 010 DVDD = 2.7V to 3.6V, VM2CP<2:0> = 011 Including internal current (Table 32) DVDD = 2.7V, AVDD = 4V, 39kHz clock 39 40 25 80 50 1.8 2.85 3.75 4.80 25 250 78 3.0 4.0 5.0 3.6 3.20 4.30 5.40 mA A kHz ns % V V SYMBOL CONDITIONS VREFADC = 2.5V IDRIVEMIN = 4A, IDRIVEMAX = 68A Not including ADC current (Note 3) 307 clocks per measurement, master clock = 5.00MHz MIN TYP 1/8 17:1 100 65 A s MAX UNITS C/LSB
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = 1.8V to 3.6V, AVDD = 2.7V to 5.5V, VREFDAC = VREFADC = 2.5V, external reference; 10F capacitor at REFADC and REFDAC; 0.01F capacitor at REFADJ; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Turn-On Time INTERNAL OSCILLATOR Clock Frequency Turn-Off Delay Turn-On Time Supply Current SWITCHES (SPDT) On Resistance On-Resistance Match On-Resistance Flatness Analog Voltage Range Turn-On/-Off Time Leakage Current Off Isolation Charge Injection Input Capacitance OPERATIONAL AMPLIFIER (RL = 10k, CL = 200pF) Input Bias Current Input Offset Voltage Input Offset Drift Common-Mode Rejection Ratio Phase Margin Charge-Pump Output Feedthrough Common-Mode Input Voltage Range No load Output Voltage Range 10k load 100k load Gain Bandwidth Product Slew Rate OSW_ Switch Resistance OSW_ Switch Turn-On/-Off Time AVDD = 2.7V to 5.5V AVDD = 4.5V to 5.5V AGND AGND 0.1 0.1 1 0.5 140 90 50 200 120 VOS VOS CMRR AGND + 100mV < VCM < AVDD - 100mV (Note 2) 0.3 2 10 75 60 100 AVDD AVDD AVDD - 0.1 AVDD - 0.1 MHz V/s ns V 1 20 nA mV V/C dB degrees VP-P V Break-before-make for SPDT configuration AGND + 100mV < VSN_ < AVDD - 100mV (Note 2) f = 10kHz Over analog voltage range AGND 50 0.08 100 1 2 1 AVDD = 2.7V to 5.5V AVDD = 4.5V to 5.5V 140 90 15 12 AVDD 200 120 V ns nA dB pC pF (Note 7) TA = TMIN to TMAX Using clock at CLKIO pin, ODLY = 1 3.5758 3.6864 1024 200 120 3.7970 MHz Clocks ns A SYMBOL CONDITIONS AVDD = 2.7V, enabled by VM2CP<1:0> MIN TYP 2 MAX UNITS ms
MAX1329/MAX1330
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = 1.8V to 3.6V, AVDD = 2.7V to 5.5V, VREFDAC = VREFADC = 2.5V, external reference; 10F capacitor at REFADC and REFDAC; 0.01F capacitor at REFADJ; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER OSW_ Switch Charge Injection Input Noise Voltage Density Input Noise Voltage Power-Down Output Leakage Power-Supply Rejection Ratio Supply Current per Amplifier Turn-On Time Short-Circuit Current DC Output Impedance DIGITAL INPUTS (DIN, SCLK, CS) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current DIGITAL OUTPUTS (DOUT, RST1, RST2) Output Low Voltage VOL ISINK = 1mA, DVDD = 2.7V to 3.6V ISINK = 200A, DVDD = 1.8V to 3.6V ISOURCE = 0.2mA, DVDD = 2.7V to 3.6V Output High Voltage VOH ISOURCE = 100A, DVDD = 1.8V to 3.6V DOUT Three-State Leakage DOUT Three-State Capacitance RST1, RST2 Open-Drain Output Low Voltage RST1, RST2 Open-Drain Output Leakage Current DIGITAL I/O (DPIO1-DPIO4, CLKIO) Output Low Voltage ISINK = 2mA, DVDD = 2.7V to 3.6V ISINK = 1mA, DVDD = 1.8V to 3.6V ISOURCE = 2mA, DVDD = 2.7V to 3.6V Output High Voltage ISOURCE = 1mA, DVDD = 1.8V to 3.6V 0.8 x DVDD 0.8 x DVDD 0.4 0.4 V (Note 2) ISINK = 1mA, DVDD = 2.7V to 3.6V ISINK = 200A, DVDD = 1.8V to 3.6V (Note 2) 0.13 0.8 x DVDD 0.8 x DVDD 0.01 10 15 0.4 0.4 100 0.4 0.4 V VIH VIL DVDD = 3V VIN = 0 or DVDD 200 0.01 10 0.7 x DVDD 0.3 x DVDD V V mV A Source Sink AV = 1V/V AVDD = 2.7V to 5.5V (Note 3) 65 100 70 5 50 13 0.2 fIN_ = 1kHz fIN_ = 0.1Hz to 10Hz SYMBOL CONDITIONS MIN TYP 1 330 9 10 MAX UNITS pC nV/Hz VRMS nA dB A s mA
V
A pF V nA
V
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(DVDD = 1.8V to 3.6V, AVDD = 2.7V to 5.5V, VREFDAC = VREFADC = 2.5V, external reference; 10F capacitor at REFADC and REFDAC; 0.01F capacitor at REFADJ; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Input High Voltage DPIO1-DPIO4 Input Low Voltage CLKIO Input Hysteresis Three-State Leakage Three-State Capacitance DPIO_ Pullup Resistance ANALOG I/O (APIO1-APIO4) Output Low Voltage ISINK = 2mA, AVDD = 2.7V to 5.5V ISINK = 1mA, AVDD = 1.8V to 5.5V ISOURCE = 2mA, AVDD = 2.7V to 5.5V Output High Voltage ISOURCE = 1mA, AVDD = 1.8V to 5.5V AVDD = 2.7V to 5.5V Input High Voltage AVDD = DVDD = 1.8V to 3.6V AVDD = 2.7V to 5.5V Input Low Voltage AVDD = DVDD = 1.8V to 3.6V Input Hysteresis Three-State Leakage Three-State Capacitance Pullup Resistance POWER REQUIREMENTS DVDD Supply Voltage Range AVDD Supply Voltage Range Supply Current (Note 8) Shutdown Current Run (all on, except charge pump) Sleep (1.8V or 2.7V monitor on) All off 1.8 2.7 3.75 1 0.5 3.6 5.5 7.5 2.5 1 V V mA A A (Note 2) 0.5 AVDD = 3V AVDD = 5V 120 160 0.01 10 15 0.8 x AVDD 0.8 x AVDD 0.7 x AVDD 0.7 x AVDD 0.3 x AVDD 0.3 x AVDD 0.4 0.4 V (Note 2) 0.5 DVDD = 3V 110 0.01 1 15 SYMBOL CONDITIONS MIN 0.7 x DVDD 0.3 x DVDD 0.25 x DVDD TYP MAX UNITS V
MAX1329/MAX1330
V
mV A pF M
V
V
V
mV A pF M
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
TIMING CHARACTERISTICS
(DVDD = 1.8V to 3.6V, AVDD = 2.7V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN 0 50 15 0 20 24 24 15 0 20 20 0 100 30 0 40 48 48 30 0 40 40 50 55 40 100 150 50 10 TYP MAX 20 UNITS MHz ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SERIAL-INTERFACE TIMING PARAMETERS (DVDD = 2.7V to 3.6V) (Figures 1 and 2) fOP SCLK Operating Frequency SCLK Cycle Time DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK Pulse-Width High SCLK Pulse-Width Low tCYC tDS tDH tDO tDV tTR tCSS tCSH tCH tCL
SERIAL-INTERFACE TIMING PARAMETERS (DVDD = 1.8V to 3.6V) (Figures 1 and 2) fOP SCLK Operating Frequency SCLK Cycle Time DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK Pulse-Width High SCLK Pulse-Width Low tCYC tDS tDH tDO tDV tTR tCSS tCSH tCH tCL
DIGITAL PROGRAMMABLE I/O TIMING PARAMETERS (DPIO1-DPIO4, DVDD = 2.7V to 3.6V, CL = 20pF) tSD SPI Write to DPIO Output Valid From last SCLK rising edge DPIO Rise/Fall Input to Interrupt Asserted Delay DPIO Input to Analog Block Delay tDI tDA Interrupt programmed on RST1 and/or RST2, corresponding status bits unmasked When controlling ADC, DACs, or switches
DIGITAL PROGRAMMABLE I/O TIMING PARAMETERS (DPIO1-DPIO4, DVDD = 1.8V to 3.6V, CL = 20pF) tSD SPI Write to DPIO Output Valid From last SCLK rising edge DPIO Rise/Fall Input to Interrupt Asserted Delay DPIO Input to Analog Block Delay tDI tDA Interrupt programmed on RST1 and/or RST2, corresponding status bits unmasked When controlling ADC, DACs, or switches
ANALOG PROGRAMMABLE I/O TIMING PARAMETERS (APIO1-APIO4, DVDD = 2.7V to 3.6V, AVDD = 2.7V to 5.5V, CL = 20pF) tSD SPI Write to APIO Output Valid From last SCLK rising edge 50 ns APIO Rise/Fall Input to Interrupt Asserted Delay CS to APIO4 Propagation Delay tDI tDCA Interrupt programmed on RST1 and/or RST2, corresponding status bits unmasked AP4MD<1:0> = 11 50 35 ns ns
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
TIMING CHARACTERISTICS (continued)
(DVDD = 1.8V to 3.6V, AVDD = 2.7V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK to APIO3 Propagation Delay DIN to APIO2 Propagation Delay APIO1 to DOUT Propagation Delay SPI-Mode Propagation Delay Matching SYMBOL tDSA tDDA tDAD tDM CONDITIONS AP3MD<1:0> = 11, CS is high AP2MD<1:0> = 11, CS is high AP1MD<1:0> = 11, CS is high Among APIO4, APIO3, APIO2, and APIO1 MIN TYP MAX 30 25 20 10 UNITS ns ns ns ns
MAX1329/MAX1330
ANALOG PROGRAMMABLE I/O TIMING PARAMETERS (APIO1-APIO4, DVDD = 1.8V to 3.6V, AVDD = 2.7V to 5.5V, CL = 20pF) tSD SPI Write to APIO Output Valid From last SCLK rising edge 100 ns APIO Rise/Fall Input to Interrupt Asserted Delay CS to APIO4 Propagation Delay SCLK to APIO3 Propagation Delay DIN to APIO2 Propagation Delay APIO1 to DOUT Propagation Delay SPI-Mode Propagation Delay Matching tDI tDCA tDSA tDDA tDAD tDM Interrupt programmed on RST1 and/or RST2, corresponding status bits unmasked AP4MD<1:0> = 11 AP3MD<1:0> = 11, CS is high AP2MD<1:0> = 11, CS is high AP1MD<1:0> = 11, CS is high Among APIO4, APIO3, APIO2, and APIO1 175 60 50 50 80 30 ns ns ns ns ns ns
Note 1: ADC INL and DNL, offset, and gain are tested at DVDD = 1.8V, AVDD = 2.7V, fSAMPLE = 234ksps to guarantee performance at fSAMPLE = 312ksps, DVDD 2.7V and AVDD 5.0V. Note 2: Guaranteed by design. Not production tested. Note 3: AVDD supply current contribution for this module. Note 4: DNL and INL are measured between code 115 and 4095. Note 5: Temperature sensor accuracy is tested using a 2.5084V reference applied to REFADJ. Note 6: The maximum trip levels for the AVDD monitor are 5% below the typical charge-pump output value. The charge-pump output voltage and the trip thresholds track to prevent tripping at -5% below the typical charge-pump output value. Note 7: DVDD supply current contribution for this module. Note 8: The normal operation and sleep mode supply currents are measured with no load on DOUT, SCLK idle, and all digital inputs at DGND or DVDD. CLKIO runs in normal mode operation and idle in sleep mode.
______________________________________________________________________________________
11
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Typical Operating Characteristics
(AVDD = 5.0V, VREFADC = VREFDAC = 2.5V for DVDD = 3.0V; TA = +25C, unless otherwise noted.)
STATIC DIGITAL SUPPLY CURRENT vs. DIGITAL SUPLY VOLTAGE (EVERYTHING ON)
MAX1329 toc01
STATIC DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE (ONLY VM1A ON)
MAX1329 toc02
STATIC DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE (SHUTDOWN)
1.75 1.50 IDVDD (A)
MAX1329 toc03
1.0
2.00 1.75 1.50 IDVDD (A) 1.25 1.00 0.75 0.50 TA = +85C TA = +25C TA = -40C
2.00
0.8 TA = +85C
TA = -40C TA = +25C
IDVDD (mA)
0.6
1.25 1.00 0.75 0.50 0.25 0 TA = +85C
0.4
TA = +25C TA = -40C
0.2 0.25 0 1.5 2.0 2.5 3.0 3.5 DVDD (V) 4.0 4.5 5.0 5.5 0 1.5 2.0 2.5 3.0 3.5 DVDD (V) 4.0 4.5 5.0 5.5
1.5
2.0
2.5
3.0
3.5 DVDD (V)
4.0
4.5
5.0
5.5
STATIC ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE (EVERYTHING ON)
1.65 1.60 IAVDD (mA)
MAX1329 toc04
STATIC ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE (ONLY VM1A AND VM1B ON)
MAX1329 toc05
STATIC ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE (SHUTDOWN)
MAX1329 toc06
1.70
1000 TA = +85C 800 TA = +25C
1000 TA = +85C
800
1.50 1.45 1.40 1.35 1.30 2.5 3.0 3.5 4.0 AVDD (V) 4.5 5.0 5.5 TA = +25C
400 TA = -40C
IAVDD (nA)
TA = -40C
IAVDD (nA)
1.55
TA = +85C
600
600
TA = +25C
400 TA = -40C
200
200
0 2.5 3.0 3.5 4.0 AVDD (V) 4.5 5.0 5.5
0 2.5 3.0 3.5 4.0 AVDD (V) 4.5 5.0 5.5
fOSC ERROR vs. DIGITAL SUPPLY VOLTAGE
MAX1329 toc07
ADC INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX1329 toc08
ADC INTEGRAL NONLINEARITY vs. TEMPERATURE
fCONV = 312ksps
MAX1329 toc09
1.0 0.8 0.6 fOSC ERROR (%) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
NOMINAL fOSC = 3.6864MHz (0% VALUE)
0.8 0.7 0.6 INL (LSB)
fCONV = 234ksps
0.8 0.7 0.6
TA = +25C
AVDD = 2.7V 0.5 AVDD = 5.5V 0.4
INL (LSB)
TA = +85C
0.5 0.4
AVDD = 5.5V AVDD = 5.0V
TA = -40C 0.3 0.2 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 DVDD (V) -40 -15 10
AVDD = 5.0V
0.3 0.2
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
12
______________________________________________________________________________________
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(AVDD = 5.0V, VREFADC = VREFDAC = 2.5V for DVDD = 3.0V; TA = +25C, unless otherwise noted.)
ADC DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (AVDD = 3.0V)
MAX1329 toc10
MAX1329/MAX1330
ADC INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (AVDD = 3.0V)
0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 90 0 1024 2048 3072 4096 2.5 IAVDD (A) fSAMPLE = 234ksps
MAX1329 toc11
ADC SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX1329 toc12
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0
1.0
fSAMPLE = 234ksps
120 115 110 105 100 95
1024
2048
3072
4096
3.0
3.5
4.0 AVDD (V)
4.5
5.0
5.5
DIGITAL INPUT CODE
DIGITAL INPUT CODE
ADC SUPPLY CURRENT vs. CONVERSION RATE
MAX1329 toc13
ADC OFFSET VOLTAGE vs. TEMPERATURE
MAX1329 toc14
ADC OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1329 toc15
400 350 300 IAVDD (A) 250 200 150 100 50 D 0 0 50 100 150 200 250 CONVERSION RATE (ksps) B = NORMAL MODE AVDD = 5V, VREFDAC = 2.5V E = NORMAL MODE AVDD = 3V, VREFADC = 1.25V 300 E F A B C
0.5
0.50
0.4 OFFSET (mV) AVDD = 2.7V
0.48 OFFSET (mV)
0.3
AVDD = 5.5V
0.46
0.2
0.44
0.1
0.42
0 -40 -15 10 35 60 85 TEMPERATURE (C) C = BURST MODE AVDD = 5V, VREFDAC = 2.5V F = BURST MODE AVDD = 3V, VREFADC = 1.25V
0.40 2.7 3.7 AVDD (V) 4.7
A = FAST POWER-DOWN AVDD = 5V, VREFDAC = 2.5V D = FAST POWER-DOWN AVDD = 3V, VREFADC = 1.25V
______________________________________________________________________________________
13
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Typical Operating Characteristics (continued)
(AVDD = 5.0V, VREFADC = VREFDAC = 2.5V for DVDD = 3.0V; TA = +25C, unless otherwise noted.)
ADC GAIN ERROR vs. TEMPERATURE
AV = 1
MAX1329 toc16
ADC GAIN ERROR vs. SUPPLY VOLTAGE
AV = 1
MAX1329 toc17
0.05
0.023
0.04 AVDD = 5.5V ERROR (%) 0.03
0.02 AVDD = 2.7V
GAIN ERROR (%)
0.022
0.021
0.01
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0.020 2.7 3.7 AVDD (V) 4.7
ADC 4096-POINT FFT PLOT
EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10.261kHz FS = 253.95ksps THD = 82.86dB SFDR = 84.74dB SINAD = 70.98dB
MAX1329 toc18
ADC ENOB vs. FREQUENCY
MAX1329 toc19
0 -20 -40 -60 -80 -100 -120 0 20 40 60 80 100 120 FREQUENCY (kHz)
13.0 12.5 12.0 11.5 11.0 10.5 10.0 120 170 220 270 320 CONVERSION RATE (ksps)
14
______________________________________________________________________________________
VOLTAGE (dB)
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(AVDD = 5.0V, VREFADC = VREFDAC = 2.5V for DVDD = 3.0V; TA = +25C, unless otherwise noted.)
ADC REFERENCE VOLTAGE (1.25V) vs. LOAD CURRENT
A B C D VREFADC (V)
MAX1329 toc20
MAX1329/MAX1330
ADC REFERENCE VOLTAGE (2.048V) vs. LOAD CURRENT
2.054 2.052 2.050 2.048 2.046 E 2.044 F 2.042 A B C D
MAX1329 toc21
1.2520 1.2515 1.2510 VREFADC (V) 1.2505 1.2500 1.2495
2.056
E 1.2490 1.2485 1.2480 -100 0 F
100
200 300 IREFADC (A)
400
500
2.040 -100
0
100
200 IREFADC (A)
300
400
500
A: TA = -40C, AVDD = 5V, DVDD = 3V B: TA = -40C, AVDD = 3V, DVDD = 2V C: TA = +25C, AVDD = 5V, DVDD = 3V
D: TA = +25C, AVDD = 3V, DVDD = 2V E: TA = +85C, AVDD = 5V, DVDD = 3V F: TA = +85C, AVDD = 3V, DVDD = 2V
A: TA = -40C, AVDD = 5V, DVDD = 3V B: TA = -40C, AVDD = 3V, DVDD = 2V C: TA = +25C, AVDD = 5V, DVDD = 3V
D: TA = +25C, AVDD = 3V, DVDD = 2V E: TA = +85C, AVDD = 5V, DVDD = 3V F: TA = +85C, AVDD = 3V, DVDD = 2V
ADC REFERENCE VOLTAGE (2.5V) vs. LOAD CURRENT
MAX1329 toc22
ADC REFERENCE VOLTAGE (1.25V) vs. ANALOG SUPPLY VOLTAGE
1.254 1.253 1.252 VREFADC (V) TA = -40C TA = +25C
MAX1329 toc23
2.510 2.508 2.506 2.504 VREFADC (V) 2.502 2.500 2.498 2.496 2.494 2.492 2.490 -100 0 100 200 IREFADC (A) A: TA = -40C, AVDD = 5V, DVDD = 3V B: TA = -40C, AVDD = 3V, DVDD = 2V C: TA = +25C, AVDD = 5V, DVDD = 3V 300 400 E F A B C D
1.255
1.251 1.250 1.249 1.248 1.247 1.246 1.245 TA = +85C
500
2.5
3.0
3.5
4.0
4.5
5.0
5.5
AVDD SUPPLY VOLTAGE (V)
D: TA = +25C, AVDD = 3V, DVDD = 2V E: TA = +85C, AVDD = 5V, DVDD = 3V F: TA = +85C, AVDD = 3V, DVDD = 2V
______________________________________________________________________________________
15
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Typical Operating Characteristics (continued)
(AVDD = 5.0V, VREFADC = VREFDAC = 2.5V for DVDD = 3.0V; TA = +25C, unless otherwise noted.)
ADC REFERENCE VOLTAGE (2.048V) vs. ANALOG SUPPLY VOLTAGE
2.055 2.054 2.053 2.052 2.051 2.050 2.049 2.048 2.047 2.046 2.045 2.044 2.043 2.042 2.041 2.5
MAX1329 toc24
ADC REFERENCE VOLTAGE (2.5V) vs. ANALOG SUPPLY VOLTAGE
2.508 2.506 2.504 VREFADC (V)
MAX1329 toc25
ADC REFERENCE LINE TRANSIENT (VADCREF = +1.25V)
MAX1329 toc26
2.510
500mV/div TA = -40C TA = +25C TA = +85C AVDD 3V 10mV/div VADCREF 1.25V
VREFADC (V)
TA = -40C
2.502 2.500 2.498 2.496
TA = +25C TA = +85C
2.494 2.492 2.490
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1ms/div
AVDD SUPPLY VOLTAGE (V)
AVDD SUPPLY VOLTAGE (V)
ADC REFERENCE LINE TRANSIENT (VADCREF = +2.048V)
MAX1329 toc27
ADC REFERENCE LINE TRANSIENT (VADCREF = +2.5V)
MAX1329 toc28
500mV/div AVDD 3V 10mV/div VADCREF 2.048V VADCREF AVDD
500mV/div 3V 10mV/div 2.5V
1ms/div
1ms/div
ADC REFERENCE LINE TRANSIENT (VADCREF = +1.25V)
MAX1329 toc29
ADC REFERENCE LINE TRANSIENT (VADCREF = +2.048V)
MAX1329 toc30
500mV/div AVDD 5V 20mV/div 1.25V AVDD
500mV/div 5V 20mV/div
VADCREF
VADCREF
2.048V
1ms/div
1ms/div
16
______________________________________________________________________________________
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Typical Operating Characteristics (continued)
(AVDD = 5.0V, VREFADC = VREFDAC = 2.5V for DVDD = 3.0V; TA = +25C, unless otherwise noted.)
ADC REFERENCE LINE TRANSIENT (VADCREF = +2.5V)
MAX1329 toc31
ADC REFERENCE SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX1329 toc32
ADC REFERENCE TURN-ON TIME vs. ANALOG SUPPLY VOLTAGE
MAX1329 toc33
446 445 500mV/div IAVDD (A) 444 2.5V 443 2.048V 442 1.25V 441 440
10
8 TURN-ON TIME (ms) 2.5V 6 2.048V 4
AV DD
5V 20mV/div
VADCREF
2.5V
2
1.25V
0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AVDD SUPPLY VOLTAGE (V) AVDD SUPPLY VOLTAGE (V)
1ms/div
DAC INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (AVDD = 3V)
MAX1329 toc34
DAC INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (AVDD = 5V)
MAX1329 toc35
DAC DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (AVDD = 3V)
VREFDAC = 2.5V 1.5 1.0 DNL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0
MAX1329 toc36
2.0 1.5 1.0 INL (LSB)
VREFDAC = 2.5V
2.0 1.5 1.0 INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0
VREFDAC = 2.5V
2.0
0.5 0 -0.5 -1.0 -1.5 -2.0 0 500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE
0 500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE
0 500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE
DAC DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (AVDD = 5V)
VREFDAC = 2.5V
MAX1329 toc37
DAC SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
75 70 65 60 55 50 45 40 VREFDAC = 2.5V, DACA VREFDAC = 2.5V, DACB OFFSET (mV) IAVDD (A)
MAX1329 toc38
DAC OFFSET VOLTAGE vs. TEMPERATURE
AVDD = 5.5V
MAX1329 toc39
2.0 1.5 1.0 DNL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0
80
2.60 2.40 2.20 2.00 1.80 1.60 AVDD = 2.7V 1.40 1.20
35 30 500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE 2.5 3.0 3.5 4.0 AVDD (V) 4.5 5.0 5.5
-40
-15
10
35
60
85
TEMPERATURE (C)
______________________________________________________________________________________
17
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Typical Operating Characteristics (continued)
(AVDD = 5.0V, VREFADC = VREFDAC = 2.5V for DVDD = 3.0V; TA = +25C, unless otherwise noted.)
DAC GAIN ERROR vs. TEMPERATURE
MAX1329 toc40
DAC SLEW RATE/CROSSTALK TRANSIENT RESPONSE (VREFDAC = +1.25V)
MAX1329 toc41
DAC SLEW RATE/CROSSTALK TRANSIENT RESPONSE (VREFDAC = +2.048V)
MAX1329 toc42
-0.800 -0.825 -0.850 ERROR (%) -0.875 -0.900 -0.925 -0.950 -0.975 -1.000 -40 -15 10 35 60 AVDD = 2.7V
AVDD = +5.0V 1.25V VOUTA 1V/div VOUTA
AVDD = +5.0V
2.048V 1V/div
VOUTB AVDD = 5.5V
1mV/div VOUTB
1mV/div
85
4s/div
4s/div
TEMPERATURE (C)
DAC SLEW RATE/CROSSTALK TRANSIENT RESPONSE (VREFDAC = +2.5V)
MAX1329 toc43
DAC DIGITAL FEEDTHROUGH TRANSIENT RESPONSE (VREFDAC = +2.50V)
MAX1329 toc44
2.5V VOUTA 1V/div 0V VSCLK VOUTB 1mV/div VOUTA
AVDD = +5.0V
2V/div
20mV/div
AVDD = +5.0V 4s/div 200ns/div
OP-AMP INPUT OFFSET VOLTAGE vs. TEMPERATURE
MAX1329 toc45
OP-AMP INPUT OFFSET VOLTAGE vs. COMMON-MODE VOLTAGE
9 8 7 VOS (mV) 6 5 4 AVDD = 3V AVDD = 5V
MAX1329 toc46
10 9 8 7 VOS (mV) 6 5 4 3 2 1 0 -40 -15 10 35 60 AVDD = 3V AVDD = 5V VCM = AVDD/2
10
3 2 1 0 85 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCM (V)
TEMPERATURE (C)
18
______________________________________________________________________________________
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(AVDD = 5.0V, VREFADC = VREFDAC = 2.5V for DVDD = 3.0V; TA = +25C, unless otherwise noted.)
OP-AMP SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX1329 toc47
MAX1329/MAX1330
OP-AMP PSRR vs. FREQUENCY
AVDD = 5.0V 70 60 PSRR (dB) 50 40 30 20 AVDD = 3.0V
MAX1329 toc48
OP-AMP OUTPUT IMPEDANCE vs. FREQUENCY
450 400 IMPEDANCE () 350 300 250 200 150 100 50 0
MAX1329 toc49
100 95 90 85 IAVDD (A) 80 75 70 65 60 55 50 2.5 3.0 3.5 4.0 AVDD (V) 4.5 5.0
80
500
5.5
0.01
0.1
10 FREQUENCY (kHz)
1
100
1000
0
1
10 FREQUENCY (kHz)
100
1000
OP-AMP MAXIMUM OUTPUT VOLTAGE vs. TEMPERATURE
MAX1329 toc50
OP-AMP MAXIMUM OUTPUT VOLTAGE vs. TEMPERATURE
AVDD/2 RL TO AVDD/2 120 100 80 60 40 20 0 E D F B A
MAX1329 toc51
50 RL TO AVDD/2 40 AVDD - VOUT (mA)
140
30
A
B
AVDD - VOUT (mA)
C
20 C 10 E 0 F D
85 10 35 60 TEMPERATURE (C) A: = RL = 5k, AVDD = 5V, DVDD = 3V B: = RL = 5k, AVDD = 3V, DVDD = 2V C: = RL = 10k, AVDD = 5V, DVDD = 3V D: = RL = 10k, AVDD = 3V, DVDD = 2V E: = RL = 100k, AVDD = 5V, DVDD = 3V F: = RL = 100k, AVDD = 3V, DVDD = 2V -15
-40
10 35 60 85 TEMPERATURE (C) A: = RL = 5k, AVDD = 5V, DVDD = 3V B: = RL = 5k, AVDD = 3V, DVDD = 2V C: = RL = 10k, AVDD = 5V, DVDD = 3V D: = RL = 10k, AVDD = 3V, DVDD = 2V E: = RL = 100k, AVDD = 5V, DVDD = 3V F: = RL = 100k, AVDD = 3V, DVDD = 2V
-40
-15
______________________________________________________________________________________
19
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Typical Operating Characteristics (continued)
(AVDD = 5.0V, VREFADC = VREFDAC = 2.5V for DVDD = 3.0V; TA = +25C, unless otherwise noted.)
OP-AMP GAIN AND PHASE vs. FREQUENCY
GAIN AVDD = 5V, 3V CL = 0pF, 220pF
MAX1329 toc52
ANALOG SWITCH ON-RESISTANCE vs. COM VOLTAGE (AVDD = 3V)
MAX1329 toc53
ANALOG SWITCH ON-RESISTANCE vs. COM VOLTAGE (AVDD = 5V)
115 TA = +25C 110 RON () 105 100 95 90 TA = +85C
MAX1329 toc54
60 30 GAIN/PHASE (dB/deg) 0 PHASE
140 135 130 125 RON () 120 115 110 105 TA = +25C TA = +85C
120
-30 -60 -90 -120 -150 -180 0.1 1 10
AVDD = 5V CL = 0pF AVDD = 3V CL = 0pF AVDD = 3V CL = 220pF
AVDD = 3V CL = 220pF 1000
100 95 90 0
TA = -40C 85 80 0.5 1.0 1.5 2.0 2.5 3.0 1
TA = -40C
100
2
3
4
5
6
FREQUENCY (kHz)
COM VOLTAGE (V)
COM VOLTAGE (V)
ANALOG SWITCH TURN-ON/-OFF TIME vs. ANALOG SUPPLY VOLTAGE
MAX1329 toc55
ANALOG SWITCH TURN-ON/-OFF TIME vs. TEMPERATURE
RL = 1k 70 60 tON/tOFF (ns) 50 40 30 20 tOFF, AVDD = 3V tON, AVDD = 5V ILEAKAGE (pA) tON, AVDD = 3V
MAX1329 toc56
ANALOG SWITCH LEAKAGE CURRENT vs. TEMPERATURE
180 160 140 120 100 80 60 40 OFF LEAKAGE
MAX1329 toc57
70 RL = 1k 60 50 tON/tOFF (ns) 40 30 20 10 0 2.5 3.0 3.5 4.0 AVDD (V) 4.5 5.0 tOFF, DVDD = 3V tOFF, DVDD = 2V tON, DVDD = 3V tON, DVDD = 2V
80
200
10 0 5.5 -40 -15
tOFF, AVDD = 5V 10 35 60 85
20 0 -40 -15 10
ON LEAKAGE 35 60 85
TEMPERATURE (C)
TEMPERATURE (C)
ANALOG SWITCH ON-RESPONSE vs. FREQUENCY
MAX1329 toc58
ANALOG SWITCH CROSSTALK AND OFF ISOLATION vs. FREQUENCY (AVDD = 3V)
MAX1329 toc59
ANALOG SWITCH CROSSTALK AND OFF ISOLATION vs. FREQUENCY (AVDD = 5V)
-50 -60 OFF ISOLATION (dB) -70 OFF ISOLATION -80 -90 -100 -110 -120 -130 CROSSTALK
MAX1329 toc60
-40 -50 -60 OFF ISOLATION (dB) -70 -80 -90 -100 -110 -120 -130 CROSSTALK OFF ISOLATION
-40
4 2 0 GAIN (dB) -2 AVDD = 3V -4 -6 -8 -10 0 0.1 1 FREQUENCY (kHz) 10 AVDD = 5V
100
0.1
1
10
100
1000
10,000
0.1
1
10
100
1000
10,000
FREQUENCY (kHz)
FREQUENCY (kHz)
20
______________________________________________________________________________________
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Typical Operating Characteristics (continued)
(AVDD = 5.0V, VREFADC = VREFDAC = 2.5V for DVDD = 3.0V; TA = +25C, unless otherwise noted.)
TEMPERATURE-SENSOR ACCURACY vs. TEMPERATURE
MAX1329 toc61
TEMPERATURE-SENSOR THERMAL STEP RESPONSE (+25C TO +85C)
MAX1329 toc62
INTERNAL TEMPERATURE-SENSOR SUPPLY CURRENT vs. SUPPLY VOLTAGE
115 110 IAVDD (A) 105 100 95 90 85 INTERNAL 2.5V REFERENCE CLKIO = 3.6864MHz ADC CLOCK DIV = 1 CONVERSION RATE = 4ksps
MAX1329 toc63
1.5 1.0 0.5 ERROR (C) INTERNAL 0 -0.5 EXTERNAL -1.0 -1.5 -40 -15 10 35 60
100 = 11s 80 TEMPERATURE (C)
120
60
40
20
0 85 -5 15 35 55 TIME (s) 75 95 115 TEMPERATURE (C)
80 2.5 3.0 3.5 4.0 AVDD (V) 4.5 5.0 5.5
CHARGE-PUMP EFFICIENCY vs. OUTPUT CURRENT (AVDD = 3V)
MAX1329 toc64
CHARGE-PUMP EFFICIENCY vs. OUTPUT CURRENT (AVDD = 4V)
MAX1329 toc65
CHARGE-PUMP EFFICIENCY vs. OUTPUT CURRENT (AVDD = 5V)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 DVDD = 3.6V DVDD = 2.7V DVDD =3.0V DVDD = 3.3V
MAX1329 toc66
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 5 10 15 20 DVDD = 1.8V DVDD = 2.0V DVDD = 2.5V DVDD = 3.0V
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 DVDD = 2.2V DVDD = 2.5V DVDD = 3.0V DVDD = 3.6V
100
25
0
5
10
15
20
25
0
5
10
15
20
25
IOUT (mA)
IOUT (mA)
IOUT (mA)
CHARGE-PUMP OUTPUT VOLTAGE vs. OUTPUT CURRENT (AVDD = 3V)
MAX1329 toc67
CHARGE-PUMP OUTPUT VOLTAGE vs. OUTPUT CURRENT (AVDD = 4V)
4.1 DVDD = 3.6V 4.0 AVDD (V) DVDD = 3.0V
MAX1329 toc68
3.2 3.1 3.0 AVDD (V) DVDD = 2.5V 2.9 2.8 2.7 2.6 2.5 0 5 DVDD = 1.8V DVDD = 2.0V DVDD = 3.0V
4.2
3.9 3.8 3.7 DVDD = 2.5V 3.6 3.5 DVDD = 2.2V
10 15 20 25 30 35 40 45 50 IOUT (mA)
0
5
10 15 20 25 30 35 40 45 50 IOUT (mA)
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21
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Typical Operating Characteristics (continued)
(AVDD = 5.0V, VREFADC = VREFDAC = 2.5V for DVDD = 3.0V; TA = +25C, unless otherwise noted.)
CHARGE-PUMP OUTPUT VOLTAGE vs. OUTPUT CURRENT (AVDD = 5V)
MAX1329 toc69
CHARGE-PUMP RIPPLE (IOUT = 5mA, DVDD = 2V, CHARGE-PUMP CLOCK = 78kHz)
MAX1329 toc70
CHARGE-PUMP LOAD TRANSIENT RESPONSE FOR 0.1mA TO 1.0mA LOAD
MAX1329 toc71
5.2 5.1 5.0 AVDD (V) 4.9 4.8 4.7 4.6 4.5 0 5 DVDD = 2.7V DVDD = 3.6V
AVDD = +3.0V, DVDD = +2.0V
AVDD = +3.0V, DVDD = +2.0V
AVDD DVDD = 3.3V DVDD = 3.0V
2mV/div
AVDD 1mA 1mV/div 0 1ms/div
IAVDD
10 15 20 25 30 35 40 45 50 IOUT (mA)
4s/div
CHARGE-PUMP LINE TRANSIENT RESPONSE FOR +2.0V TO +2.5V STEP INPUT
MAX1329 toc72
CHARGE-PUMP SUPPLY CURRENT vs. SUPPLY VOLTAGE
380
MAX1329 toc73
400
AVDD = +3.0V, 3.0k LOAD DVDD 2.5V 500mV/div 2V
360 340 IDVDD (A) 320 300 280 260 240 220 200 AVDD = 3.0V
AVDD = 5V
AVDD = 4.0V
AVDD
100mV/div
2ms/div
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DVDD (V)
22
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
Pin Description
PIN MAX1329 1 2 3 4 5 MAX1330 1 2 3 4 5 NAME DPIO1 DPIO2 DPIO3 DPIO4 DOUT Digital Programmable Input/Output 1 Digital Programmable Input/Output 2 Digital Programmable Input/Output 3 Digital Programmable Input/Output 4 Serial-Data Output. DOUT outputs serial data from the data register. DOUT changes on the falling edge of SCLK and is valid on the rising edge of SCLK. When CS is high, DOUT is high impedance, unless APIO1 is programmed for SPI mode. Serial-Clock Input. Apply an external serial clock to transfer data to and from the device. When CS is high, SCLK is inactive unless APIO3 is configured for SPI mode. Then the input on SCLK is level-shifted and output at APIO3. Serial-Data Input. Data on DIN is clocked in on the rising edge of SCLK when CS is low. When CS is high, DIN is inactive unless APIO2 is configured for SPI mode. Then the input on DIN is level-shifted and output at APIO2. Active-Low Chip-Select Input. Drive CS low to transfer data to and from the device. When CS is high and APIO4 is configured for SPI mode, APIO4 is low. Open-Drain Reset Output 1. RST1 remains low while DVDD is below 1.8V. RST1 can be reprogrammed as a push-pull, active-high, or active-low Status register interrupt output. Open-Drain Reset Output 2. RST2 remains low while DVDD is below 2.7V. RST2 can be reprogrammed as a push-pull, active-high, or active-low Status register interrupt output. Analog Programmable Input/Output 1 Analog Programmable Input/Output 2 Analog Programmable Input/Output 3 Analog Programmable Input/Output 4 Analog Switch 1 Normally-Open Terminal Analog Switch 1 Common Terminal Analog Switch 1 Normally-Closed Terminal Operational Amplifier 1 Noninverting Input Operational Amplifier 1 Inverting Input. Also internally connected to ADC mux. Operational Amplifier 1 Output. Also internally connected to ADC mux. No Connection. Not internally connected. DACB Force-Sense Feedback Input. Also internally connected to ADC mux. DACB Force-Sense Output. Also internally connected to ADC mux. Operational Amplifier 2 Noninverting Input Operational Amplifier 2 Inverting Input. Also internally connected to ADC mux. Operational Amplifier 2 Output. Also internally connected to ADC mux. FUNCTION
MAX1329/MAX1330
6
6
SCLK
7
7
DIN
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 -- -- --
8 9 10 11 12 13 14 15 16 17 18 19 20 -- -- -- 21 22 23
CS RST1 RST2 APIO1 APIO2 APIO3 APIO4 SNO1 SCM1 SNC1 IN1+ IN1OUT1 N.C. FBB OUTB IN2+ IN2OUT2
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23
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Pin Description (continued)
PIN MAX1329 24 25 MAX1330 24 25 NAME OUTA FBA FUNCTION DACA Force-Sense Output. Also internally connected to ADC mux. DACA Force-Sense Feedback Input. Also internally connected to ADC mux. DAC Internal Reference Buffer Output/DAC External Reference Input. In internal reference mode, REFDAC provides a 1.25V, 2.048V, or 2.5V internal reference buffer output. In external DAC reference buffer mode, disable internal reference buffer. Bypass REFDAC to AGND with a 1F capacitor. Analog Switch 2 Normally-Closed Terminal Analog Switch 2 Common Terminal Analog Switch 2 Normally-Open Terminal Analog Input 2. Also internally connected to ADC mux. Analog Input 1. Also internally connected to ADC mux. ADC Internal Reference Buffer Output/ADC External Reference Input. In internal reference mode, REFADC provides a 1.25V, 2.048V, or 2.5V internal reference buffer output. In external ADC reference buffer mode, disable internal reference buffer. Bypass REFADC to AGND with a 1F capacitor. Internal Reference Output/Reference Buffer Amplifiers Input. In internal reference mode, bypass REFADJ to AGND with a 0.01F capacitor. In external reference mode, disable internal reference. Analog Ground Analog Supply Input. Bypass AVDD to AGND with at least a 0.01F capacitor. With the charge pump enabled, see Table 32 for required capacitor values. Charge-Pump Capacitor Input B. Connect CFLY across C1A and C1B. See Table 32 for required capacitor values. Charge-Pump Capacitor Input A. Connect CFLY across C1A and C1B. See Table 32 for required capacitor values. Digital Supply Input. Bypass DVDD to DGND with at least a 0.01F capacitor. When using charge pump, see Table 32 for required capacitor values. Digital Ground Clock Input/Output. In internal clock mode, enable CLKIO output for external use. In external clock mode, apply a clock signal at CLKIO for the ADC and charge pump. Exposed Pad. The exposed pad is located on the package bottom and is internally connected to AGND. Connect EP to the analog ground plane. Do not route any PCB traces under the package.
26
26
REFDAC
27 28 29 30 31
27 28 29 30 31
SNC2 SCM2 SNO2 AIN2 AIN1
32
32
REFADC
33 34 35 36 37 38 39 40
33 34 35 36 37 38 39 40
REFADJ AGND AVDD C1B C1A DVDD DGND CLKIO
--
--
EP
24
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
CS tCSH tCSS SCLK tCL tCYC tCH tCSH
tDS DIN
tDH
tDV DOUT
tDO
tTR
Figure 1. Detailed Serial-Interface Timing Diagram
Detailed Description
The MAX1329/MAX1330 smart DASs are based on a 312ksps, 12-bit SAR ADC with a 1ksps, 16-bit DSP mode. The ADC includes a differential multiplexer, a programmable gain amplifier (PGA) with gains of 1, 2, 4, and 8, a 20-bit accumulator, internal dither, a 16-word FIFO, and an alarm register. The MAX1329/MAX1330 operate with a digital supply down to 1.8V and feature an internal charge pump to boost the supply voltage for the analog circuitry that requires 2.7V to 5.5V. The MAX1329/MAX1330 include an internal reference with programmable buffer for the ADC, two analog external inputs as well as inputs from other internal circuitry, an internal/external temperature sensor, internal oscillator, dual single-pole, double-throw (SPDT) switches, four digital programmable I/Os, four analog programmable I/Os, and dual programmable voltage monitors. The MAX1329 features dual 12-bit force-sense DACs with programmable reference buffer and one operational amplifier. The MAX1330 includes one 12-bit forcesense DAC with programmable reference buffer and dual op amps. DACA can be sequenced with a 16-word FIFO. The DAC buffers and op amps have internal analog switches between the output and the inverting input.
DVDD
3k DOUT 3k DOUT
CLOAD = 20pF
CLOAD = 20pF
a) FOR ENABLE, HIGH IMPEDANCE b) FOR ENABLE, HIGH IMPEDANCE TO VOH AND VOL TO VOH. TO VOL AND VOH TO VOL. FOR DISABLE, VOH TO HIGH IMPEDANCE. FOR DISABLE, VOL TO HIGH IMPEDANCE.
Figure 2. DOUT Enable and Disable Time Load Circuits
Register Bit Descriptions section for the default values after a power-on reset.
Power-On Setup
After applying power to AVDD: 1) Write to the Reset register. This initializes the temperature sensor and voltage reference trim logic. 2) Within 3ms following the reset, configure the charge pump as desired by writing to the CP/VM Control register. The details of programming the charge pump are described in the Charge Pump section.
Power-On Reset
After a power-on reset, the DVDD voltage supervisor is enabled with thresholds at 1.8V and 2.7V. All digital and analog programmable I/Os (DPIOs and APIOs) are configured as inputs with pullups enabled. The internal oscillator is enabled and is output at CLKIO once the 1.8V reset trip threshold has been exceeded and the subsequent timeout period has expired. See the
Charge Pump
Power AVDD and DVDD by any one of the following ways: drive AV DD and DV DD with a single external power supply, drive AV DD and DV DD with separate external power supplies, or drive DVDD with an external supply and enable the internal charge pump to generate AVDD or short DVDD to AVDD internally.
25
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
INTERNAL OSCILLATOR 4.9152MHz (OFF, ON) CLOCK OUTPUT DIVIDER (OFF, /1, /2, /4) OSCE = 1
DPIO configured as SLP or SHDN inputs. In normal mode, each analog and digital block can be powered up or shut down individually through its respective control register.
CLKIO
Voltage Supervisors
The MAX1329/MAX1330 provide two programmable voltage supervisors, one for DVDD and one for AVDD. The DVDD voltage supervisor has two thresholds (set to 1.8V and 2.7V by default) that are both enabled after a poweron reset. On initial power-up, RST1 is assigned the 1.8V monitor output and RST2 is assigned the 2.7V monitor output, both for DVDD. If DVDD falls below the 1.8V or 2.7V threshold, the VM1A bit or VM1B bit, respectively, in the Status register is set. The VM1A and VM1B status bits can also be mapped to the interrupt generator. The default states of RST1 and RST2 are open-drain outputs but can be programmed as push-pull Status register interrupts through the CP/VM Control register. The AVDD voltage supervisor provides three programmable thresholds. If AVDD falls below the programmed threshold, the VM2 bit is set in the Status register. The VM2 status bit can also be mapped to the interrupt generator.
CLOCK INPUT DIVIDER (OFF, /1, /2, /4) OSCE = 0
MUX
OSCE
1
0
CHARGE-PUMP CLOCK DIVIDER (/32, /64, /128, /256)
CHARGE PUMP (OFF, 3V, 4V, 5V)
ADC CLOCK DIVIDER (/1, /2, /4, /8)
MUX
ADC (ACQUIRE CLKS) (ADC CONTROL) (ADC SETUP)
SCLK
Interrupt Generator
Figure 3. Clock-Divider Block Diagram
Upon a power-on reset, the charge pump is disabled. Enable the charge pump through the CP/VM Control register. When the charge pump is in its off state, AVDD is isolated from DV DD unless the bypass switch is enabled. To bypass the charge pump and directly connect DVDD to AVDD, enable (close) the bypass switch through the CP/VM Control register (see Tables 21 and 22). During the on mode, the charge pump boosts DVDD and regulates the voltage to generate the selected output voltage at AVDD. The charge-pump output voltage selections are 3.0V, 4.0V, or 5.0V. The charge-pump clock and ADC clock are synchronized from the same master clock. The charge pump uses a pulse-width-modulation (PWM) scheme to regulate the output voltage. The charge pump supports a maximum load of 25mA of current to an external device including what is required for internal circuitry.
The interrupt generator accepts inputs from other internal circuits to provide an interrupt to an external microcontroller (C). The sources for generating an interrupt are programmable through the serial interface. Possible sources include a rising or falling edge on the digital and analog programmable inputs, ADC alarms, an ADC conversion complete, an ADC FIFO full, an ADC accumulator full, and the voltage-supervisor outputs. The interrupt causes RST1 and/or RST2 to assert when configured as an interrupt output. The interrupt remains asserted until the Status register is read. See the CP/VM Control register for programming the RST1 and RST2 outputs as interrupts and the Interrupt Mask register for programming the interrupt sources.
Internal Oscillator and Programmable Clock Dividers
The MAX1329/MAX1330 feature an internal oscillator, which operates at a fixed frequency of 3.6864MHz. When enabled, the internal oscillator provides the master clock source for the ADC and charge pump. To allow external devices to use the internally generated clock, configure CLKIO as an output through the Clock Control register. The CLKIO output frequency is configurable for 0.9216MHz, 1.8432MHz, and 3.6864MHz. When the internal oscillator is enabled, and regardless of the CLKIO output frequency, the ADC and charge-pump clock dividers always receive a 3.6864MHz clock signal (see Figure 3). After a power-on reset, CLKIO defaults to an output with the divider set to 2 (resulting in 1.8432MHz).
Power Modes
Three power modes are available for the MAX1329/ MAX1330: shutdown, sleep, and normal operation. In shutdown mode, all functional blocks are powered down except the serial interface, data registers, and wake-up circuitry (if enabled). Sleep mode is identical to shutdown mode except the DVDD voltage monitors (if enabled) remain active. Global sleep or shutdown mode is initiated through a
26
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
For external clock mode, disable the internal oscillator, which then configures CLKIO as an input. Apply an external clock at CLKIO with a frequency up to 20MHz. The input clock divider can be set to 1, 2, or 4. The output of the CLKIO input divider goes to the input of charge pump and ADC clock dividers. Note: When using the internally generated clock, entering shutdown or sleep mode causes CLKIO to become an input. To prevent crowbar current, connect a 500k resistor from CLKIO to DGND.
MAX1329/MAX1330
Table 1. Temperature vs. ADC Output
TEMPERATURE (C) +85.000 +70.000 +25.000 +0.250 +0.125 0 -0.125 -0.250 -25.000 -40.000 ADC OUTPUT DATA TWO'S COMPLEMENT 0010 1010 1000 0010 0011 0000 0000 1100 1000 0000 0000 0010 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 1111 0011 1000 1110 1100 0000 HEX 2A8 230 0C8 002 001 000 FFF FFE F38 EC0
Digital and Analog Programmable I/Os
The MAX1329/MAX1330 provide four digital programmable I/Os (DPIO1-DPIO4) and four analog programmable I/Os (APIO1-APIO4). The DPIOs and APIOs can be configured as logic inputs or outputs through the DPIO and APIO Control registers. The DPIOs are powered by DVDD. Likewise, the APIOs are powered by AVDD. When configured as inputs, internal pullups can be enabled through the DPIO and APIO Setup registers.
where ADC output data is the decimal value of the two's complement result. The MAX1329/MAX1330 support external single-ended and differential temperature measurements using a diode connected transistor between AIN1 and AGND, AIN2 and AGND, or AIN1 and AIN2. Select the appropriate channel for conversion through the ADC Setup register.
Digital Programmable I/O DPIO1-DPIO4 are powered by DVDD and are programmable as the following: * General-purpose input * Wake-up input (internal oscillator enable) * Power-down mode (sleep or shutdown) control input * DAC loading or sequencing input * ADC acquisition and conversion control input * DAC, op amp, and SPDT switch control input * ADC data-ready output * General-purpose output Analog Programmable I/O APIO1-APIO4 are powered by AVDD and are programmable as the following: * General-purpose input * Wake-up input (internal oscillator enable) * General-purpose output * Digital input/output for signals to be level-shifted from/to the SPI interface
Voltage References
The internal unbuffered 2.5V reference is externally accessible at REFADJ. Separate ADC and DAC reference buffers are programmable to output 1.25V, 2.048V, or 2.5V REFADC and REFDAC. The reference and buffers can be individually controlled through the ADC Control and DAC Control registers. Power down the internal reference to apply an external reference at REFADJ as an input to the ADC and DAC reference buffers. Power down the reference buffers to apply external references directly at REFADC and REFDAC. Note: All temperature sensor measurements use the voltage at REFADJ as a reference and require a 2.5V reference for accurate results.
Operational Amplifiers
The MAX1329 includes one uncommitted operational amplifier. The MAX1330 includes two op amps. These op amps feature rail-to-rail inputs and outputs, with a bandwidth of 1MHz. The op amps are powered down through the DAC Control register. An internal analog switch shorts the negative input to the output when enabled through the Switch Control register or a DPIO configured as a switch control input. When powered down, the outputs of the op amps go high impedance.
Temperature Sensor
An internal temperature sensor measures the device temperature of the MAX1329/MAX1330. The ADC converts the analog measurement from the internal temperature sensor to a digital output (see Table 1). The temperature measurement resolution is +0.125C for each LSB and the measured temperature can be calculated using the following equation: T = ADC output data/8C
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27
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Single-Pole/Double-Throw (SPDT) Switches
The MAX1329/MAX1330 provide two uncommitted SPDT switches that can also be configured as a doublepole/single-throw (DPST) switch (see Tables 28 and 29). Each switch has a typical on-resistance of 115 at AVDD = 3V. The switch is controlled through the Switch Control register or a DPIO configured to control the switches.
ADC FIFO WRITE POINTER 0 1 2 3 4 5 6 7 DEPTH POINTER 8 9 10 11 12 13 14 15 INTERRUPT POINTER READ POINTER
Analog-to-Digital Converter (ADC)
The MAX1329/MAX1330 include a 12-bit SAR ADC with a programmable-gain amplifier (PGA), input multiplexer, and digital post-processing. The analog input signal feeds into the differential input multiplexer and then into the PGA with gain settings of 1, 2, 4, or 8. The temperature sensor and supply voltage measurements bypass the PGA. Both unipolar and bipolar transfer functions are selectable. The ADC done status bit (ADD in the Status register) can be programmed to provide an interrupt. Any of the DPIOs can be configured as a CONVST input to directly control the acquisition time and synchronize the conversions. A 16-word FIFO stores the ADC results until the 12-bit data is read by the external C.
Figure 4. ADC FIFO
Analog Inputs The MAX1329/MAX1330 provide two external analog inputs: AIN1 and AIN2. The inputs are rail-to-rail and can be used differentially or single-ended to ground. The analog inputs can also be used for remote temperature sensing with external diodes. AIN1 and AIN2 feed directly into a differential multiplexer. This 16-channel multiplexer is segmented into an upper and a lower multiplexer (see Tables 7 and 8 for configuration). ADC FIFO Register The ADC writes its results in the ADC FIFO, which stores up to sixteen 16-bit words. Each 16-bit word in the FIFO includes a 4-bit FIFO address and the 12-bit data result from the ADC. The ADC FIFO includes four pointers: depth, interrupt, write, and read configured by writing to the ADC FIFO register (see Figure 4). A depth pointer sets the working depth of the FIFO such that locations beyond the depth pointer are inaccessible for writing or reading. The interrupt pointer sets the location that causes an interrupt every time data has been written to that location. Set the interrupt pointer to the same or lower location than the depth pointer. The interrupt pointer is set equal to the depth pointer if written with a value greater than the depth pointer. A write to the ADC FIFO register causes the write and read pointers to reset to location 0. Setting the depth pointer to location 0 disables the FIFO.
28
Every time a conversion completes, the data is written to the present location of the write pointer, which then increments by 1. The write pointer continues to increment until the depth pointer location has been written. The write pointer then moves to location 0 and continues to increment but must remain behind the read pointer. Once the last valid FIFO location has been written, no further ADC results are written to the FIFO until the next FIFO location is cleared by a read. When the ADC FIFO is enabled, the read pointer points to location 0. When a read occurs, the pointer then increments by 1 only if 15 of the 16 bits are clocked out successfully. Reading the FIFO is done in 16-bit words consecutively as long as a serial clock is present. The read pointer must stay one location behind the write pointer. When the write pointer is one location ahead of the read pointer and the read continues, it clocks out the current read location over and over again until the write pointer increments. The FIFO can be accessed simultaneously by the serial interface to read a result and by the ADC to write a result, but the read and write pointers are never at the same address.
ADC Accumulator, Decimation, and Dither Mode The accumulator is used for oversampling. In this mode, up to 256 samples are accumulated in the ADC Accumulator register. This is a 24-bit read register with 1 bit for dither enable, 3 bits for the accumulator count, and 20 bits for the accumulated ADC conversions. The
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
VREFADC/GAIN 1111 1111 1111 1111 1111 1110 TWO'S COMPLEMENT OUTPUT CODE 1111 1111 1101 1111 1111 1100 BINARY OUTPUT CODE 1 LSB = VREFADC (GAIN x 4096) FULL-SCALE TRANSITION 0111 1111 1111 0111 1111 1110 0111 1111 1101 VREFADC (GAIN x 4096) VREFADC (2 x GAIN) -1 0 +1 +2045 +2047 VREFADC (2 x GAIN) -2046 INPUT VOLTAGE (LSB) VREFADC (2 x GAIN) VREFADC (2 x GAIN)
1 LSB = 0000 0000 0001 0000 0000 0000 1111 1111 1111
0000 0000 0011 0000 0000 0010 0000 0000 0001 0000 0000 0000 0 1 2 3 INPUT VOLTAGE (LSB) 4093 4095
VREFADC/GAIN
1000 0000 0010 1000 0000 0001 1000 0000 0000 -2048
Figure 5. Unipolar Transfer Function
Figure 6. Bipolar Transfer Function
accumulator is functional for the normal, fast powerdown, and burst modes, but cannot be used for temperature-sensor conversions. The 20-bit binary accumulator provides up to 256 times oversampling and binary digital filtering. The digital filter has a sinc response and the notch locations are determined by the sampling rate and the oversampling ratio (see the Applying a Digital Filter to ADC Data Using the 20-Bit Accumulator section). There is a digital-signalprocessing mode where dither is added to the oversampling to extend the resolution from 12 to 16 bits. In this mode, a sample rate of 1220sps can be maintained. The oversampling rate (OSR) required to achieve an increase in resolution is OSR = 22N, where N is the additional bits of resolution. See the ADC Accumulator Register section.
format is binary for unipolar mode and two's complement for bipolar mode. Calculate 1 LSB using the following equation: 1 LSB = VREFADC/(gain x 4096) for both unipolar and bipolar modes, where VREFADC is the reference voltage at REFADC and gain is the PGA gain. In unipolar mode, the output code ranges from 0 to 4095 for inputs from zero to fullscale. In bipolar mode, the output code ranges from -2048 to +2047 for inputs from negative full-scale to positive full-scale.
Digital-to-Analog Converter (DAC)
The MAX1329 includes two 12-bit DACs (DACA and DACB) and the MAX1330 includes one 12-bit DAC (DACA). The DACs feature force-sense outputs and DACA includes a 16-word FIFO. Each DAC is doublebuffered with an input and output register (see Figure 7). The DACA(B)PD<1:0> bits in the DAC Control register control the power and write modes for DACA and DACB. With the DAC(s) powered-up, the three possible commands are a write to both the input and output registers, a write to the input register only, or a shift of data from the input register to the output register. With the DAC(s) powered-down, only a simultaneous write to both input and output registers is possible. DPIO_ can be programmed to shift the input register data to the output register for each DAC individually or simultaneously (MAX1329 only). The value in the output register
29
ADC Alarm Mode The ADC Greater-Than (GT) and Less-Than (LT) Alarm registers can be used to generate an interrupt once the ADC result exceeds the alarm register value. The alarm registers also control the number of alarm trips required and whether or not they need to be consecutive to generate an interrupt. The GT and LT alarms are programmed through the ADC GT and LT Alarm registers. The alarms are functional for the normal, fast powerdown, and burst modes. ADC Transfer Functions Figures 5 and 6 provide the ADC transfer functions for unipolar and bipolar mode. The digital output code
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
FROM REFDAC
FROM SERIAL I/O
DAC INPUT REGISTER
DAC OUTPUT REGISTER
12-BIT DAC
TO DAC OUTPUT BUFFER
FIFOA CONTROL REGISTER
16-WORD DAC FIFO
DDS LOGIC
FOR DACA ONLY
Figure 7. Detailed DAC and FIFO Block Diagram
determines the analog output voltage. An internal switch configures the force-sense output for unity gain configuration when it is closed. In power-down mode, the DAC outputs and feedback inputs are high impedance.
16 12 8 FIFO LOCATION 4 0 -4 -8 -12 -16 0 16 32 SEQUENCE NUMBER 48 64 PHASE 1 PHASE 2 DAC INPUT REGISTER VALUE PLUS FIFO LOCATION 1 VALUE DAC INPUT REGISTER VALUE DAC INPUT REGISTER VALUE MINUS FIFO LOCATION 16 VALUE DAC INPUT REGISTER VALUE MINUS FIFO LOCATION 1 VALUE
DACA FIFO and Direct Digital Synthesis (DDS) Logic The DACA FIFO and DDS logic can be used for waveform synthesis by loading the FIFO and configuring the DDS mode through the FIFOA Control register. The FIFO is sequenced by writing to the FIFO Sequence register address or by toggling a DPIO configured for this function. The input register value, in conjunction with the FIFOA Data register values, can be used to create waveforms. The FIFOA Data register values are added to or subtracted from the Input register value before shifting to the output register. The FIFO data is straight binary (0 to +4095) when the bipolar bit (BIPA) is not asserted and as sign magnitude (-2047 to +2047) when BIPA is asserted. In sign magnitude mode, the MSB represents the sign bit, where 0 indicates a positive number and 1 indicates a negative number. The 11 LSBs provide the magnitude in sign magnitude. The type of waveform generated is determined by the asymmetric/symmetric mode bit (SYMA), unipolar/bipolar mode bit (BIPA), and the single/continuous mode bit (CONA). All waveforms are generated in phases (see Figure 8). For all bit combinations, phase 1 is created by first shifting the input register value to the output reg30
PHASE 3 PHASE 4
Figure 8. DAC FIFO Waveform Phases
ister. For each subsequent sequence, the FIFOA Data register value is added to the input register before shifting to the output register until the programmed FIFO depth has been reached (see Figure 9a). The FIFO depth (DPTA<3:0>) can be set to any integer value from 1 to 16 and the FIFO always starts at location 1. Asserting the SYMA bit creates phase two by causing the FIFO to reverse direction at the end of phase 1 without repeating the final value before sequencing back to the beginning (see Figure 9c).
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
(a) OUTPUT WAVEFORM (UNIPOLAR, ASYMMETRIC, SINGLE)
16 16
(b) OUTPUT WAVEFORM (UNIPOLAR, ASYMMETRIC, CONTINUOUS)
16
(c) OUTPUT WAVEFORM (UNIPOLAR, SYMMETRIC, SINGLE)
12 FIFO LOCATION FIFO LOCATION
12 FIFO LOCATION
12
8
8
8
4
4
4
0 0 16 32 48 64 80 96 112 128 SEQUENCE NUMBER
0 0 16 32 48 64 80 96 112 128 SEQUENCE NUMBER
0 0 16 32 48 64 80 96 112 128 SEQUENCE NUMBER
(d) OUTPUT WAVEFORM (UNIPOLAR, SYMMETRIC, CONTINUOUS)
16 16 12 12 FIFO LOCATION FIFO LOCATION 8 4 0 -4 -8 -12 0 0 16 32 48 64 80 96 112 128 SEQUENCE NUMBER -16 0
(e) OUTPUT WAVEFORM (UNIPOLAR, ASYMMETRIC, SINGLE)
16 12 8 FIFO LOCATION 16 32 48 64 80 96 112 128 4 0 -4 -8 -12 -16
(f) OUTPUT WAVEFORM (BIPOLAR, ASYMMETRIC, CONTINUOUS)
8
4
0
16
32
48
64
80
96
112 128
SEQUENCE NUMBER
SEQUENCE NUMBER
(g) OUTPUT WAVEFORM (BIPOLAR, SYMMETRIC, SINGLE)
16 12 8 FIFO LOCATION 4 0 -4 -8 -12 -16 0 16 32 48 64 80 96 112 128 SEQUENCE NUMBER FIFO LOCATION 16 12 8 4 0 -4 -8 -12 -16
(h) OUTPUT WAVEFORM (BIPOLAR, SYMMETRIC, CONTINUOUS)
0
16
32
48
64
80
96
112 128
SEQUENCE NUMBER
Figures 9a-9h. Waveform Examples Using the DAC FIFO
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Table 2. Direct-Mode Definitions
COMMAND NAME ADC Convert DACA Write DACB Write Register Mode* START 1 0 0 0 1 1 0 R/W R/W R/W 0 1 ADDRESS (ADR<4:0>) MUX<3:0> CONTROL GAIN<1:0> DACA<11:0> DACB<11:0> DATA (D<255:0>, D<23:0>, D<15:0>, or D<7:0>) BIP
*See Table 3.
Asserting the BIPA bit with SYMA = 1 creates phases three and four (see Figure 9g). Phases three and four repeat the same sequence as in phases one and two, respectively, but the FIFO data is subtracted from the input register data this time through. The final value in phase two is not repeated before proceeding with phase three. The resulting waveform is composed of all four phases. Asserting the BIPA bit with SYMA = 0 creates phase four (see Figure 9e). Phase four repeats the same sequence as in phase one in reverse order, but the FIFO data is subtracted from the input register data. In this case, the last location in the FIFO is repeated before sequencing back to the beginning. When the CONA bit is not asserted, the output is static once the end of the programmed pattern has been reached. Asserting the CONA bit causes the patterns described above to repeat without repeating the final value (see Figures 9b, 9d, 9f, and 9h). The FIFO Enable bit (FFEA) enables the ability to create waveforms. The FFEA must be disabled to write to the FIFOA Data register. Any change in the FIFOA Control register reinitializes the FIFO sequencing logic and the next sequence loads the input register value. The DACA Input and/or Output registers can be written directly and not affect the sequencing logic. Writing to the DACA input register effectively moves the DC offset of the waveform on the next sequence and writing to the DACA output register immediately changes the output level independent of the FIFO.
falling edge of SCLK. The serial interface is compatible with SPI modes CPOL = 0, CPHA = 0 and CPOL = 1, CPHA = 1. A write operation takes effect on the rising edge of SCLK used to shift in the LSB (or last bit of the data word being written). If CS goes high before the complete transfer, the write is ignored. CS must be forced high between commands.
Direct-Mode Commands The direct-mode commands include the ADC Convert command and DACA and DACB Read and Write commands. The ADC Convert command is an 8-bit command that initiates an ADC conversion, selects the conversion channel through the multiplexer, sets the PGA gain, and selects bipolar or unipolar mode. If an ADC Convert command is issued during a conversion in progress, the current conversion aborts and a new one begins. The MUX<3:0>, GAIN<1:0>, and BIP bits settings in the ADC Setup register are overwritten by the values in the ADC Convert command. The DACA and DACB Data Write commands set the DACA and DACB input and/or output register values, respectively. The DACA and DACB data write modes are determined by the DAC Control register. The DACA and DACB data read commands read the DACA and DACB input register data, respectively. In register mode, an address byte identifies each register. The data registers are 8, 16, or 24 bits wide. The ADC and DACA FIFO Data registers are variable length up to 256 bits wide. Figures 10-17 provide example timing diagrams for various commands. ADC Conversion Timing Configure the ADC Control and Setup registers before attempting any conversions. Initiate an ADC conversion with the 8-bit ADC Convert command (see Table 2) or by toggling a DPIO input configured for an ADC conversion-start function. When a conversion completes, the result is ready to be read in the data register. In burst mode, the ADC data is delivered real time on DOUT.
Serial Interface
The MAX1329/MAX1330 feature a 4-wire serial interface consisting of a chip select (CS), serial clock (SCLK), data in (DIN), and data out (DOUT). CS must be low to allow data to be clocked into or out of the shift register. DOUT is high-impedance while CS is high, unless APIO1 is programmed for SPI mode. The data is clocked in at DIN into the shift register on the rising edge of SCLK. Data is clocked out at DOUT on the
32
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
CS
SCLK
DIN DOUT
X
0
0
0
A4
A3
A2
A1
A0
DN-1
DN -2
DN-3
DN-4
D2
D1
D0
X
X = DON'T CARE.
Figure 10. Variable Length Register-Mode Data-Write Operation
CS
SCLK
DIN
X
0
0
1
A4
A3
A2
A1
A0
X
X
X
X
X
X
X
X
DOUT X = DON'T CARE.
DN-1
DN-2
DN-3
DN-4
D2
D1
D0
Figure 11. Variable Length Register-Mode Data-Read Operation
CS
SCLK
DIN
X
1
M3
M2
M1
M0
G1
G0
BIP
X
X
0
0
1
0
0
0
1
0
X
X
X
X
X
DOUT
D N-1 D N-2
D1
D0
X = DON'T CARE.
Figure 12. Write Command to Start a Normal or Fast Power-Down ADC Conversion Followed by ADC Data Register Read
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
CS
SCLK
DIN
X
0
1
0
AB
D 11
D 10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
DOUT
X = DON'T CARE.
Figure 13. Write to DACA (AB = 0) or DACB (AB = 1). The DAC Control register programs the write mode.
CS
SCLK
DIN
X
0
1
1
AB
X
X
X
X
X
X
X
X
X
X
X
X
X
DOUT
D 11
D 10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X = DON'T CARE.
Figure 14. Read of DACA (AB = 0) or DACB (AB = 1) Input Register
RST1/RST2*
INTERRUPT ASSERTED
REASSERTS IF NEW INTERRUPT OCCURS DURING READ
CS
SCLK
DIN
X
X
X
0
0
1
1
0
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
DOUT
D 23
D 22
D1
D0
*RST1 AND RST2 ARE ACTIVE-HIGH (INTP = 1). X = DON'T CARE.
Figure 15. Read of Status Register to Clear Asserted Interrupt (RST1/RST2)
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
CS
SCLK
DIN
X
0
1
0
AB
D 11
D 10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DAC
PREVIOUS OUTPUT
NEW OUTPUT
DPIO X = DON'T CARE.
RISING EDGE TRIGGERED
Figure 16. Write to DACA (AB = 0) or DACB (AB = 1) Input Register Followed by a DPIO DACA or DACB Load
CS
WRITE TO MAX1329/MAX1330 TO ENABLE SPI MODE
WRITE THROUGH MAX1329/MAX1330 TO APIO DEVICE
NORMAL WRITE TO MAX1329/MAX1330
SCLK
DIN
DN
D N-1 D N-2 D N-3
D3
D2
D1
D0
EN
E N-1 E N-2 E N-3
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
E3
E2
E1
E0
APIO4
SET BY APIO CONTROL REGISTER
INVERTED CS
APIO3
SET BY APIO CONTROL REGISTER EN E N-1 E N-2 E N-3
SET TO GPO
APIO2
SET BY APIO CONTROL REGISTER
X
X
X
X
SET TO GPO
APIO1
SET BY APIO CONTROL REGISTER X = DON'T CARE.
E3
E2
E1
E0
SET TO GPI
Figure 17. Write to Program and Use APIO SPI Mode
The four conversion modes programmed by the APD<1:0> and AUTO<2:0> bits in the ADC Control register are: autoconvert, fast power-down, normal, and burst modes. In normal and fast power-down modes, single conversions are initiated with the ADC convert command or by toggling a configured DPIO. In fast power-down mode, the PGA and ADC power down between conversions to reduce power. A minimum of 16 clock cycles is required to complete a conversion in normal or fast power-down mode.
Burst mode is initiated with one ADC convert command and continuously converts on the same channel sending the data directly to DOUT as long as there is activity on SCLK and CS is low. Burst mode aborts when CS goes high. In burst mode, SCLK directly clocks the ADC. For best performance, synchronize SCLK with the CLKIO clock (see Figure 18). A minimum of 14 clock cycles is required to complete a conversion in burst mode.
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 X
20 X
21 X
22
23 X
24
25 X
DIN
X
1
M3
M2
M1
M0
G1
G0
BIP
X
X
X
X
X
X
X
X
X
X
X
X
DOUT
D 11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D 11
ADC MODE
TRACK
CONVERT
TRACK
CONVERT
ADCDONE* *ADCDONE IS AN INTERNAL SIGNAL. RISING EDGE OF ADCDONE SETS THE ADD BIT IN THE STATUS REGISTER. X = DON'T CARE.
Figure 18. Write Command to Start ADC Burst Conversions Clocked by SCLK with Real-Time Data Read (ACQCK<1:0> = 00, GAIN<1:0> = 00)
CS
SCLK
1
2
3
4
5
6
7
8
DIN
X
1
M3
M2
M1
M0
G1
G0
BIP
CLKIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
ADC MODE
TRACK
CONVERT
PD*
ADCDONE** *PD IS AN INTERNAL SIGNAL. WHEN PD IS HIGH, THE ADC IS POWERED-DOWN. **ADCDONE IS AN INTERNAL SIGNAL. RISING EDGE ADCDONE SETS THE ADD BIT IN THE STATUS REGISTER. X = DON'T CARE.
Figure 19. Write Command to Start ADC Normal or Fast Power-Down, with Autoconvert Disabled (AUTO<2:0> = 000) and Conversions Clocked by CLKIO (OSCE = 0, ADDIV<1:0> = 00, CLKIO<1:0> = 11)
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
Once configured, autoconvert mode initiates with one ADC Convert command. Conversions continue at the rate selected by the ADC Autoconvert bits (see Table 4) until disabled by writing to the ADC Control register. The Autoconvert mode can run only in the normal or fast power-down modes. The autoconvert function must be disabled to use burst mode or DPIO CONVST mode. When writing to the ADC Control register in fast powerdown mode with autoconvert disabled, acquisition begins on the 1st rising ADC clock edge after CS transitions high, and ends after the programmed number of clock cycles. The conversion completes a minimum 14 clock cycles after acquisition ends. When autoconvert is enabled, an additional three ADC clock cycles are added prior to acquisition to allow the ADC to wake up. See Figures 19 and 20 for timing diagrams.
MAX1329/MAX1330
CS
SCLK
1
2
3
4
5
6
7
8
DIN
X
1
M3
M2
M1
M0
G1
G0
BIP
CLKIO
1
2
3
4
5
6
7
8
9
10
11
12
13
18
19
ADC MODE
TRACK
CONVERT
PD*
ADCDONE** *PD IS AN INTERNAL SIGNAL. WHEN PD IS HIGH, THE ADC IS POWERED DOWN. **ADCDONE IS AN INTERNAL SIGNAL. RISING EDGE ADCDONE SETS THE ADD BIT IN THE STATUS REGISTER. X = DON'T CARE.
Figure 20. Write Command to Start ADC Normal or Fast Power-Down, with Autoconvert Enabled and Conversions Clocked by CLKIO (OSCE = 0, ADDIV<1:0> = 00, CLKIO<1:0> = 11)
CLKIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
ADC MODE
TRACK
CONVERT
TRACK
CONVERT
DPIO (CONVST)
EDGE TRIGGERED
PD*
ADCDONE** *PD IS AN INTERNAL SIGNAL. WHEN PD IS HIGH, THE ADC IS POWERED DOWN. **ADCDONE IS AN INTERNAL SIGNAL. RISING EDGE ADCDONE SETS THE ADD BIT IN THE STATUS REGISTER. ADDIV = 00.
Figure 21. DPIO-Controlled ADC Conversion Start
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
CS TEMP CONVERT COMMAND (SCLK, DIN, DOUT NOT SHOWN) THERE ARE TWO ADC CONVERSIONS PER TEMPERATURE CONVERSION.
WAIT PERIOD 93.5 CLOCKS
1ST AQUISITION 90 CLOCKS
1ST CONVERSION 19 CLOCKS
2ND AQUISITION 87 CLOCKS
2ND CONVERSION 17.5 CLOCKS
ADC MODE
TRACK
CONVERT
TRACK
CONVERT
1 CLOCK = 1/(ADC MASTER CLOCK FREQUENCY) START STOP
Figure 22. Temperature-Conversion Timing
See Figure 21 for performing an ADC conversion using a DPIO input programmed as CONVST. Allow at least 600ns for acquisition while the DPIO input is low and the acquisition ends on the rising edge of the DPIO. The conversion requires an additional 14 ADC clock cycles. If the PGA gain is set to 4 or 8, the minimum acquisition time is 1.2s due to the increase of the input sampling capacitor.
q = charge of electron = 1.602 10-19 coulombs k = Boltzman constant = 1.38 10-23 J/K n = ideality factor (slightly greater than 1) The temperature measurement process is fully automated in the MAX1329/MAX1330. All steps are sequenced and executed by the MAX1329/MAX1330 each time an input channel (or an input channel pair) configured for temperature measurement is scanned. The resulting 12-bit, two's complement number represents the sensor temperature in degrees Celsius, with 1 LSB = +0.125C. Figure 22 shows the timing for a temperature measurement. An external 2.500V reference can be applied to REFADJ, provided the internal reference is disabled first. Use the temperature correction equation to obtain the correct temperature: TACT = 0.997 x TMEAS - 0.91C Use the following equation when using the internal reference: TACT = TMEAS + (TMEAS + 270.63) x (1 - 2.500V )C VREFADJ
Temperature Measurement
The MAX1329/MAX1330 perform temperature measurement by measuring the voltage across a diode-connected transistor at two different current levels. The following equation illustrates the algorithm used for temperature calculations: q k temperature = (VHIGH - VLOW) x IHigh n x ln ILOW where: VHIGH = sensor-diode voltage with high current flowing (IHIGH) VLOW = sensor-diode voltage with low current flowing (ILOW)
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
Register Definitions
MAX1329/MAX1330
Table 3. Register Summary
REGISTER NAME ADC Control ADC Setup ADC Data ADC FIFO ADC Accumulator ADC GT Alarm ADC LT Alarm DAC Control FIFOA Control Reserved FIFOA Data Reserved FIFO Sequence Clock Control CP/VM Control Switch Control APIO Control APIO Setup DPIO Control DPIO Setup Status START 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ/ WRITE (R/W) R/W R/W 1 0 1 0 1 R/W R/W R/W R/W X R/W X W R/W R/W R/W R/W R/W R/W R/W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 ADDRESS (ADR<4:0>) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 DITH DITH GTAM LTAM DATA (D<255:0>, D<23:0>, D<15:0>, OR D<7:0>) AUTO<2:0> MSEL ADCDATA<11:0> AFFD<3:0> AFFDATA<11:0>* ACCC<2:0> ACCC<2:0> GTAC<2:0> LTAC<2:0> X APD<1:0> MUX<3:0> X AREF<1:0> GAIN<1:0> X X AFFI<3:0> AFFA<3:0>* X X X ACCDATA<19:0> GTAT<11:0> LTAT<11:0> DREF<1:0> REFE REFE BIP X
DBPD0/ DAPD0/ OA1E DBPD1 1 DAPD1 OA2E OA3E 0 1 0 1 0 1 0 1 0 1 0 1 0 MV1A X ODLY INTP DSWA/ OSW3 X OSCE FFAE BIPA
SYMA CONA DPTA<3:0> RESERVED, DO NOT USE X X X VM2CP<2:0> OSW2 SPDT1<1:0> AP2MD<1:0> AP3LL X X X X X X RESERVED, DO NOT USE X CLKIO<1:0> ADDIV<1:0> ACQCK<1:0> CPDIV<1:0> SPDT2<1:0> AP1MD<1:0> AP2LL AP1LL
FFADATA<11:0>
VM1<1:0> DSWB OSW1
AP4MD<1:0>
AP3MD<1:0>
AP4PU AP3PU AP2PU AP1PU AP4LL DP4MD<3:0> DP2MD<3:0> VM1A VM1B VM2 ADD AFF
DP3MD<3:0> DP1MD<3:0> DP2LL GTA DP1LL LTA ACF
DP4PU DP3PU DP2PU DP1PU DP4LL DP3LL APR<4:1> DPR<4:1> MV1B MV2 MADD MAFF
APF<4:1> DPF<4:1> MACF MGTA MLTA MAPF<4:1> MDPF<4:1>
Interrupt Mask Reserved Reserved Reserved
0 0 0 0
0 0 0 0
R/W X X X
1 1 1 1
0 0 0 1
1 1 1 0
0 1 1 0
1 0 1 0
MAPR<4:1> MDPR<4:1>
RESERVED, DO NOT USE RESERVED, DO NOT USE RESERVED, DO NOT USE
Note: R/W = 0 for write, R/W = 1 for read, X = don't care. *Data length can vary from 1 to 16 words, where a word is 16 bits (12 data bits plus 4 address bits).
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Table 3. Register Summary (continued)
REGISTER NAME Reserved Reserved Reserved Reserved Reserved Reserved Reset START 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ/ WRITE (R/W) X X X X X X W 1 1 1 1 1 1 1 ADDRESS (ADR<4:0>) 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 X X DATA (D<255:0>, D<23:0>, D<15:0>, OR D<7:0>) RESERVED, DO NOT USE RESERVED, DO NOT USE RESERVED, DO NOT USE RESERVED, DO NOT USE RESERVED, DO NOT USE RESERVED, DO NOT USE X X X X X X
Note: R/W = 0 for write, R/W = 1 for read, X = don't care. *Data length can vary from 1 to 16 words, where a word is 16 bits (12 data bits plus 4 address bits).
Register Bit Descriptions ADC Control Register The ADC Control register configures the autoconvert mode, the ADC power-down modes, the ADC reference buffer, and the internal reference voltage. Changes made to the ADC Control register settings are applied immediately. If changes are made during a conversion in progress, discard the results of that conversion to ensure a valid conversion result. AUTO<2:0>: ADC Autoconvert bits (default = 000). The AUTO<2:0> bits configure the ADC to continuously convert at the selected interval (see Table 4). Calculate the conversion rate by dividing the ADC master clock frequency by the selected number of clock cycles. For example, if the ADC master clock frequency is 3.6864MHz and the selected value is 256, the conversion rate is 3.6864MHz/256 or 14.4ksps. The conversion can be started with the ADC Direct Write command and runs continuously using the ADC master clock. Write 000 to the AUTO<2:0> bits to disable autoconvert mode. When the autoconvert ADC master clock cycle rate is set to 32 and the acquisition time is set to 32 (AUTO<2:0> = 001, ACQCK<1:0> = 11, and GAIN<1:0> = 1X), the acquisition time is automatically reduced to 16 clocks so that the ADC throughput is less than the autoconversion interval. The automode operation is unavailable in burst mode. APD<1:0>: ADC Power-Down bits (default = 00). The APD<1:0> bits control the power-down states of the ADC and PGA (see Table 5). When a direct-mode ADC conversion command is received, the ADC and PGA power up except when APD<1:0> = 00.
MSB NAME DEFAULT AUTO2 0 AUTO1 0 AUTO0 0
The burst mode outputs data to DOUT directly in real time as the bit decision is made on the falling edge of SCLK and the latest conversion result is also stored in the ADC Data register. For this mode, the conversion rate is controlled by the SCLK frequency, which is limited to 5MHz. If the charge pump is enabled, synchronize SCLK with the CLKIO clock to prevent charge-pump noise from corrupting the ADC result. Initiate the conversion by writing to the ADC Control register. SCLK is required to run continuously during the conversion period. For ADC gains of 1 or 2, a total of 14 to 28 clocks (two to 16 for acquisition and 12 for conversion) are required to complete the conversion. For ADC gains of 4 or 8, a total of 16 to 44 clocks (four to 32 for acquisition, and 12 for conversion) are required to complete the conversion. Bringing CS high aborts burst mode. AREF<1:0>: ADC Reference Buffer bits (default = 00). The AREF<1:0> bits set the ADC reference buffer gain when REFE = 0 and the REFADC output voltage when REFE = 1 (see Table 6). Set AREF<1:0> to 00 to disable the ADC reference buffer and drive REFADC directly with an external reference. REFE: Internal Reference Enable bit (default = 0). REFE = 1 enables the internal reference and sets REFADJ to 2.5V. REFE = 0 disables the internal reference, allowing an external reference to be applied at REFADJ, which drives the inputs to the ADC and DAC reference buffers. The voltage at REFADJ is also used for temperature measurement and must be 2.5V for accurate results. See the Temperature Sensor section. This bit is mirrored in the DAC Control register so that writing either location updates both bits.
LSB APD1 0 APD0 0 AREF1 0 AREF0 0 REFE 0
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Table 4. ADC Autoconvert Bit Configuration (AUTO<2:0>)
AUT02 0 0 0 0 1 1 1 1 AUTO1 0 0 1 1 0 0 1 1 AUTO0 0 1 0 1 0 1 0 1 ADC MASTER CLOCK CYCLES Autoconvert disabled 32 64 128 256 512 1024 2048
Table 5. ADC Power-Down Bit Configuration
APD1 0 0 1 1 APD0 0 1 0 1 ADC MODE Power-down Fast power-down Normal Burst ADC/PGA off ADC/PGA off between conversions ADC/PGA on ADC/PGA on, SCLK clocks conversion, data clocked out on DOUT in real time on the falling edge of SCLK COMMENTS
Table 6. ADC Reference-Buffer Bit Configuration
AREF1 0 0 1 1 AREF0 0 1 0 1 ADC REFERENCE-BUFFER GAIN (V/V) (REFE = 0) Buffer off 0.5 0.8192 1 REFADC VOLTAGE (V) (REFE = 1) High-impedance 1.25 2.048 2.5
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
ADC Setup Register The ADC Setup register configures the input multiplexer, ADC gain, and unipolar/bipolar modes to perform a data conversion. Changes made to the ADC Setup register settings are applied immediately. If changes are made during a conversion in progress, discard the results of that conversion to ensure a valid conversion result. MSEL: Multiplexer Select bit (default = 0). The MSEL bit selects the upper or lower multiplexer. MSEL = 0 selects the upper mux and MSEL = 1 selects the lower mux.
MSB NAME DEFAULT MSEL 0 MUX3 0 MUX2 0 MUX1 0 MUX0 0 GAIN1 0 GAIN0 0
MUX<3:0>: Multiplexer Input Select bits (default = 0000). The MUX<3:0> bits plus the MSEL bit select the inputs to the ADC (see Tables 7 and 8). GAIN<1:0>: ADC Gain bits (default = 00). The GAIN<1:0> bits select the gain of the ADC (see Table 9). BIP: Unipolar-/Bipolar-Mode Selection bit (default = 0). For unipolar mode, set BIP = 0. For bipolar mode, set BIP = 1. For temperature-sensor conversions, use the default GAIN = 00 and BIP = 0.
LSB BIP 0
Table 7. Upper Multiplexer Bit Configuration (MSEL = 0)
MUX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MUX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MUX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MUX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTB FBB OUTB FBB AIN1 AIN2 OUTA FBA OUT1 IN1OUT2 IN2FBB OUTB POSITIVE INPUT MAX1329 AIN1 AIN2 OUTA FBA OUT1 IN1OUT2 IN2MAX1330 NEGATIVE INPUT MAX1329 AGND AGND AGND AGND AGND AGND AGND AGND AIN2 AIN1 FBA OUTA IN1OUT1 IN2OUT2 MAX1330
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Table 8. Lower Multiplexer Bit Configuration (MSEL = 1)
MUX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MUX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MUX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MUX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTB OUTB AIN1 OUTA OUT1 OUT2 TEMP1+ (Internal diode anode) TEMP2+ (External diode anode at AIN1) TEMP3+ (External diode anode at AIN1) TEMP4+ (External diode anode at AIN2) DVDD/4 AVDD/4 REFADC REFDAC POSITIVE INPUT MAX1329 AIN1 OUTA OUT1 OUT2 MAX1330 NEGATIVE INPUT MAX1329 REFADC REFADC REFADC REFADC REFDAC REFDAC REFDAC REFDAC TEMP1(Internal diode cathode) TEMP2(External diode cathode at AIN2) AGND AGND AGND AGND AGND AGND MAX1330
Table 9. ADC Gain Bit Configuration
GAIN1 0 0 1 1 GAIN0 0 1 0 1 ADC GAIN SETTING (V/V) 1 2 4 8
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ADC Data Register The ADC Data register contains the result from the most recently completed analog-to-digital conversion. The 12-bit result is stored in the ADCDATA<11:0> bits. The data format is binary for unipolar mode and two's complement for bipolar mode. The ADC Data register contents are the same as the ADC FIFO contents at the last written address, unless writes to the ADC FIFO have been inhibited.
MSB NAME DEFAULT ADCDATA11 ADCDATA10 0 0 ADCDATA9 0 ADCDATA8 0 ADCDATA7 0 ADCDATA6 0 ADCDATA5 0 ADCDATA4 0 LSB NAME DEFAULT ADCDATA3 0 ADCDATA2 0 ADCDATA1 0 ADCDATA0 0 X X X X X X X X
X = Don't care.
ADC FIFO Register The ADC FIFO register contents are different for write and read modes. In write mode, the ADC FIFO register sets the working depth of the FIFO and the address that generates an interrupt. In read mode, the ADC FIFO register holds the ADC FIFO data and FIFO address.
Write Format
A serial interface write to the ADC FIFO register moves the FIFO write and read pointers to address 0. AFFD<3:0>: ADC FIFO Depth bits (default = 0000). AFFD<3:0> sets the working depth of the FIFO (see Table 10). If set to a depth of zero, the ADC FIFO is disabled and writes to the AFF (ADC FIFO Full) bit in the Status register are also disabled. AFFD<3:0> are writeonly bits.
MSB NAME DEFAULT AFFD3 0 AFFD2 0 AFFD1 0
AFFI<3:0>: ADC FIFO Interrupt Address bits (default = 0000). AFFI<3:0> sets the FIFO address. After each successful ADC conversion, the conversion results are transferred from the ADC Data register to the FIFO location indicated by the FIFO write pointer, and the FIFO write pointer is incremented. When the FIFO write pointer exceeds the value in AFFI<3:0>, the AFF bit in the Status register (Table 11) is asserted. Set the AFFI<3:0> value equal to or less than the AFFD<3:0> value. If set to a value greater than AFFD<3:0>, AFFI<3:0> is forced to the AFFD<3:0> value. If AFFD<3:0> is set to 0000 (depth of zero), the ADC FIFO is disabled and writes to the AFF bit are also disabled. AFFI<3:0> are write-only bits.
LSB AFFD0 0 AFFI3 0 AFFI2 0 AFFI1 0 AFFI0 0
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Read Format
A single read from the ADC FIFO register returns the ADC FIFO data and the 4-bit FIFO address (AFFA<3:0>) corresponding to the location read. After clocking out the 16-bit word, the read pointer increments and continual clock shifts out the 16-bit word at the location pointed to by the ADC FIFO read pointer. If trying to read from the ADC FIFO at a location pointed to by the ADC FIFO write pointer, the FIFO repeats the last ADC conversion result and corresponding ADC FIFO address equivalent to the ADC FIFO write pointer. To stop reading, bring CS high after clocking out the 16th bit of a complete word. The read
MSB NAME DEFAULT AFFDATA11 0 AFFDATA10 0 AFFDATA9 0
pointer increments after each complete 16-bit word read. It does not increment if the read is aborted by bringing CS high before clocking out all 16 bits. Any read operation on the ADC FIFO register resets the interrupt flag (AFF). AFFDATA<11:0>: ADC FIFO Read Data bits (default = 0000 0000 0000). AFFDATA<11:0> returns the data written by the ADC at the current read pointer location. AFFA<3:0>: ADC FIFO Read Address bits (default = 0000). AFFA<3:0> returns the address of the current read pointer location. AFFA<3:0> is never greater than the AFFD<3:0> programmed value.
MAX1329/MAX1330
AFFDATA8 0
AFFDATA7 0
AFFDATA6 0
AFFDATA5 0
AFFDATA4 0 LSB
NAME DEFAULT
AFFDATA3 0
AFFDATA2 0
AFFDATA1 0
AFFDATA0 0
AFFA3 0
AFFA2 0
AFFA1 0
AFFA0 0
Note: Data length can vary from 1 to 16 words, where a word is 16 bits (12 data bits plus 4 address bits).
Table 10. ADC FIFO Depth Bit Configuration
AFFD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AFFD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 AFFD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 AFFD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ADC FIFO WORD DEPTH WRITE POINTER RANGE
Table 11. ADC FIFO Interrupt-Address Bit Configuration
AFFI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AFFI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 AFFI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 AFFI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ADC FIFO INTERRUPT ADDRESS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIFO disabled 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0-1 0-2 0-3 0-4 0-5 0-6 0-7 0-8 0-9 0-10 0-11 0-12 0-13 0-14 0-15
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ADC Accumulator Register The ADC Accumulator register contains the bits to enable dither, set the accumulator count, and set the 20-bit accumulator data. The dither and accumulator count bits are read/write and the accumulator data is read only. A write to the register resets the accumulator data (ACCDATA<19:0>) to 0x00000 and starts new accumulation. The ACCDATA<19:0> bits remain unchanged until the programmed count of conversions is completed. The accumulator is functional for the normal, fast power-down, and burst modes. DITH: Dither bit (default = 0). When DITH = 0, the dither generator is disabled and the accumulator can be used for oversampling and providing digital filtering (see the Applying a Digital Filter to ADC Data Using the 20-Bit Accumulator section). When DITH = 1, the dithering for the ADC is enabled. Use dithering with the accumulator to oversample data and decimate the result to extend the
Write Format
NAME DEFAULT MSB DITH 0 ACCC2 0 ACCC1 0 ACCC0 0 X X X X X X LSB X X
effective resolution to a maximum of 16 bits and provide digital filtering. ACCC<2:0> ADC Accumulator Count bits (default = 000). The ACCC<2:0> bits set the number of ADC data conversion results to be accumulated and then written to the ACCDATA register before the ACF Status bit is set (see Table 12). The ACF status bit is set in the Status register when the data is written to the ACCDATA register. If the accumulator count is set to 1, the accumulator does not accumulate and the ACCDATA<11:0> is the same as ADCDATA<11:0> in the ADC Data register. ACCDATA<19:0>: ADC Accumulator Data bits (default = 0x00000). The ACCDATA<19:0> bits are the summation of up to 256 ADC conversion results. When the count set by ACCC<2:0> has been reached, the ACF status bit is set and the accumulated data is written to this register. The data is written to the register at a rate of the ADC conversion rate divided by the accumulator count. The accumulator does not exceed 0xFFFFF.
X = Don't care.
Read Format
MSB NAME DEFAULT DITH 0 ACCC2 0 ACCC1 0 ACCC0 0 ACCDATA19 ACCDATA18 ACCDATA17 ACCDATA16 0 0 0 0
NAME DEFAULT
ACCDATA15 ACCDATA14 ACCDATA13 ACCDATA12 ACCDATA11 ACCDATA10 0 0 0 0 0 0
ACCDATA9 0
ACCDATA8 0 LSB ACCDATA0 0
NAME DEFAULT
ACCDATA7 0
ACCDATA6 0
ACCDATA5 0
ACCDATA4 0
ACCDATA3 0
ACCDATA2 0
ACCDATA1 0
Table 12. ADC Accumulator-Count Bit Configuration
ACCC2 0 0 0 0 1 1 1 1 ACCC1 0 0 1 1 0 0 1 1 ACCC0 0 1 0 1 0 1 0 1 ACCUMULATOR COUNT 1 4 8 16 32 64 128 256
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ADC GT Alarm Register The ADC GT Alarm register contains the greater-than mode, trip count, and threshold settings. A write to this register address resets the trip counters to zero. The GT alarm is functional for the normal, fast power-down, and burst modes. GTAM: ADC Greater-Than Alarm Mode bit (default = 0). GTAM = 0 means that the alarm trips do not need to be consecutive before the GTA Status bit is set. When GTAM = 1, the alarm trips must be consecutive to set the GTA Status bit.
GTAC<2:0>: ADC Greater-Than Alarm Trip Count bits (default = 000). GTAC<2:0> set the number of conversion results needed to be greater than the alarm threshold before the GTA Status bit is set (see Table 13). GTAT<11:0>: ADC Greater-Than Alarm Threshold bits (default = 0xFFF). When the required number of conversion results greater than the threshold set by the GTAT<11:0> bits have been completed, the GTA Status bit is set in the Status register. Clearing the GTA Status bit by reading the Status register or writing to the ADC GT Alarm register restarts the trip count. The GTAT<11:0> bits are in binary format when the ADC is in unipolar mode and two's complement format when the ADC is in bipolar mode. Disable the GT alarm by setting GTAT<11:0> to 0xFFF when the ADC is in unipolar mode and 0x7FF when the ADC is in bipolar mode.
MAX1329/MAX1330
MSB NAME DEFAULT GTAM 0 GTAC2 0 GTAC1 0 GTAC0 0 GTAT11 1 GTAT10 1 GTAT9 1 GTAT8 1 LSB NAME DEFAULT GTAT7 1 GTAT6 1 GTAT5 1 GTAT4 1 GTAT3 1 GTAT2 1 GTAT1 1 GTAT0 1
Table 13a. ADC Greater-Than Alarm Trip Count Bit Configuration
GTAC2 0 0 0 0 1 1 1 1 GTAC1 0 0 1 1 0 0 1 1 GTAC0 0 1 0 1 0 1 0 1 NUMBER OF TRIPS 1 2 3 4 5 6 7 8
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
ADC LT Alarm Register The ADC LT Alarm register contains the less-than mode, trip count, and threshold settings. Writing the register address resets the trip counters to zero. The LT alarm is functional for the normal, fast power-down, and burst modes. LTAM: ADC Less-Than Alarm Mode bit (default = 0). LTAM = 0 means that the alarm trips need not be consecutive to cause the LTA Status bit to be set. LTAM = 1 means that the alarm trips must be consecutive before the LTA Status bit is set.
LTAC<2:0>: ADC Less-Than Alarm Trip Count bits (default = 000). LTAC<2:0> set the number of conversion results needed to be less than the alarm threshold before the LTA Status bit is set.
MSB NAME DEFAULT LTAM 0 LTAC2 0 LTAC1 0 LTAC0 0 LTAT11 0 LTAT10 0 LTAT9 0 LTAT8 0 LSB NAME DEFAULT LTAT7 0 LTAT6 0 LTAT5 0 LTAT4 0 LTAT3 0 LTAT2 0 LTAT1 0 LTAT0 0
LTAT<11:0>: ADC Less-Than Alarm Threshold bits (default = 0x000). When the required number of ADC conversions results less than the threshold set by the LTAT<11:0> bits have been completed, the LTA Status bit is set in the Status register. Clearing the LTA Status bit by reading the Status register or writing to the ADC LT Alarm register restarts the trip count. The LTAT<11:0> bits are in binary format when the ADC is in unipolar mode and two's complement format when the ADC is in bipolar mode. Disable the LT alarm by setting LTAT<11:0> to 0x000 when the ADC is in unipolar mode and 0x800 when the ADC is in bipolar mode.
Table 13b. ADC Less-Than Alarm Trip Count Bit Configuration
LTAC2 0 0 0 0 1 1 1 1 LTAC1 0 0 1 1 0 0 1 1 LTAC0 0 1 0 1 0 1 0 1 NUMBER OF TRIPS 1 2 3 4 5 6 7 8
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DAC Control Register The DAC Control register configures the power states for DACA, DACB, the op amps, DAC reference buffer, and the internal reference. The DAC Control register also controls the DACA and DACB input and output register write modes. At power-up, all DACs and op amps are powered down. When powered down, the outputs of the DAC buffers and op amps are high impedance.
DAPD<1:0>: DACA Power-Down bits (default = 00). DAPD<1:0> control the power-down states and write modes for DACA (see Table 14). DBPD<1:0>: (MAX1329 only) DACB Power-Down bits (default = 00). DBPD<1:0> control the power-down states and write modes for a DACB write as shown in Table 15. OA1E: Op Amp 1 Enable bit (default = 0). Set OA1E = 1 to power up op amp 1. OA2E (MAX1330 only): Op Amp 2 Enable bit (default = 0). Set OA2E = 1 to power up op amp 2. DREF<1:0>: DAC Reference Buffer bits (default = 00). DREF<1:0> sets the DAC reference buffer gain when REFE = 0 (see Table 16). DREF<1:0> sets the REFDAC voltage when the REFE = 1. REFE: Internal Reference Enable bit (default = 0). REFE = 1 enables the internal reference and sets REFADJ to 2.5V. REFE = 0 disables the internal reference so an external reference can be applied at REFADJ, which drives the inputs to the ADC and DAC reference buffers. This bit is mirrored in the ADC Control register so that writing either location updates both bits.
MAX1329/MAX1330
MAX1329 MSB NAME DEFAULT MAX1330 MSB NAME DEFAULT DAPD1 0 DAPD0 0 X X OA2E 0 OA1E 0 DREF1 0 DREF0 0 LSB REFE 0 DAPD1 0 DAPD0 0 DBPD1 0 DBPD0 0 OA1E 0 DREF1 0 DREF0 0 LSB REFE 0
Table 14. DACA Power-Down Bit Configuration
DAPD1 0 0 1 1 DAPD0 0 1 0 1 DACA POWER MODE Powered down Powered up Powered up Powered up DACA WRITE MODE Write input and output register Write input and output register Write input register Shift input to output register
Table 15. DACB Power-Down Bit Configuration (MAX1329 Only)
DBPD1 0 0 1 1 DBPD0 0 1 0 1 DACB POWER MODE Powered down Powered up Powered up Powered up DACB WRITE MODE Write input and output register Write input and output register Write input register Shift input to output register
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FIFOA Control Register The FIFOA Control register enables the DACA FIFO, configures the bipolar, symmetry, and continuous modes, and sets the depth of the FIFO. Any change to the contents of this register resets the FIFOA sequence to the starting location. If the FIFO operation is enabled (FFAE = 1), the next sequence command transfers the DACA input register data to the output register. The DACA input or output register can be written to when the FIFO is enabled without affecting the FIFOA sequence, but the DACA output and/or input register data is changed. FFAE: DACA FIFO Enable bit (default = 0). Set FFAE = 1 to enable the sequencing function. FFAE must be set to 0 to write to the FIFO. Writes to the FIFO when FFAE = 1 are ignored.
BIPA: DACA FIFO Bipolar bit (default = 0). Set BIPA = 0 to generate a unipolar waveform or set BIPA = 1 to generate a bipolar waveform. For a unipolar waveform, the FIFOA data is added to the DACA input register data during phases 1 and 2 (see Figures 8 and 9). For a bipolar waveform, the FIFOA data is added to the DACA input register data (during phases 1 and 2) and
MSB NAME DEFAULT FFAE 0 BIPA 0 SYMA 0 CONA 0 DPTA3 0 DPTA2 0 DPTA1 0
subtracted from the DACA input register data (during phases 3 and 4). SYMA: DACA FIFO Symmetry bit (default = 0). Set SYMA = 0 to generate an asymmetrical waveform, consisting of phase 1 (BIPA = 0) or phases 1 and 4 (BIPA = 1). Set SYMA = 1 to generate symmetry phases 1 and 2 (BIPA = 0) or phases 1-4 (BIPA = 1). CONA: DACA FIFO Continuous bit (default = 0). Set CONA = 0 to generate a single waveform or set CONA = 1 to generate a periodic or continuous waveform. DPTA<3:0>: DACA FIFO Depth bits (default = 0000). The DPTA<3:0> bits set the depth of the FIFOA data register to be used for waveform generation (see Table 17). The entire FIFOA data register can be filled with 16 words but only the number programmed by DPTA<3:0> are used. During waveform generation, the FIFOA words are added to the DACA input register value before being sent to the DACA output register. The first output is the DACA input register value. The following value is the DACA input register value summed with the FIFOA location 1 value. The FIFOA locations are incremented until the FIFO depth specified by the DPTA<3:0> bits has been reached.
LSB DPTA0 0
Table 16. DAC Reference Buffer Bit Configuration
DREF1 0 0 1 1 DREF0 0 1 0 1 DAC REFERENCE BUFFER GAIN (V/V) (REFE = 0) N/A 0.5 0.8192 1.0 REFDAC VOLTAGE (V) (REFE = 1) Buffer disabled 1.25 2.048 2.5
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FIFOA Data Register The FIFOA Data register stores up to 16 12-bit words that can be used by DACA to generate a waveform.
FFADATA<11:0>: FIFOA Data bits (default = 0xXXX). FFADATA<11:0> represents a 12-bit word that is left justified with 4 don't-care LSBs. A write or read operation always starts at location 1 and ends at the full FIFO depth. Any attempt to write past the full FIFO depth does not overwrite the data just written. Any attempt to read past the full FIFO depth returns zeroes on DOUT.
MSB NAME DEFAULT FFADATA11 0 FFADATA10 0 FFADATA9 0 FFADATA8 0 FFADATA7 0 FFADATA6 0 FFADATA5 0 FFADATA4 0 LSB NAME DEFAULT FFADATA3 0 FFADATA2 0 FFADATA1 0 FFADATA0 0 X X X X X X X X
A write to the FIFOA Data register is possible only when the FFAE bit in the FIFOA Control register is 0. If FFAE = 1, any write to the FIFOA Data register is ignored. A read command is possible at any time. If BIPA = 0, the data is interpreted as binary (0 to 4095). If BIPA = 1, the data is interpreted as sign magnitude (-2047 to +2047). In sign magnitude, the MSB represents the sign bit, where 0 indicates a positive number and 1 indicates a negative number. The 11 LSBs provide the magnitude in sign magnitude.
MAX1329/MAX1330
X = Don't care.
Table 17. DACA FIFO Depth Bit Configuration
DPTA3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DPTA2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DPTA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DPTA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FIFOA DEPTH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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FIFO Sequence Register A write to the FIFO Sequence register steps DACA to the next FIFOA word. A valid write consists of the 8-bit address and 8 bits of data, where the data bits are don'tcare bits. The FIFO location increments on the 16th rising edge of SCLK. Successive writes sequence the entire contents of the FIFOA Data register to the DACA output register. The FIFO can also be sequenced with the DPIOs configured as DLDA or DLAB. The FIFO Sequence register is a write-only register. Clock Control Register The Clock Control register enables the internal oscillator and the CLKIO output, sets the ADC acquisition time, and controls the CLKIO, ADC, and charge-pump programmable dividers.
ODLY: Oscillator Turn-Off Delay bit (default = 0). Set ODLY = 0 to allow the oscillator to turn off immediately when powered down by the OSCE bit. If ODLY = 1, the oscillator turns off 1024 CLKIO clock cycles after it is powered down by the OSCE bit. ODLY also affects DPIO sleep mode (SLPB). When ODLY = 1, OSCE = 1, and CLKIO<1:0> does not equal 00b, SLPB is delayed by 1024 CLKIO clocks. OSCE: Internal Oscillator Enable bit (default = 1). Set OSCE = 1 to enable the internal 3.6864MHz oscillator. Set OSCE = 0 to disable the internal oscillator and apply an external oscillator at CLKIO. When turning off, CLKIO drives low before becoming an input. Do not leave CLKIO unconnected when configured as an input. The APIOs and DPIOs can be configured as a wake-up to set the OSCE bit. CLKIO<1:0>: CLKIO Configuration bits (default = 10). CLKIO<1:0> control the CLKIO input and output divider settings. See Table 18 for the CLKIO configurations. Changes to the CLKIO<1:0> bits occur on the falling edge of CLKIO. The ODLY bit is ignored and has no effect when the CLKIO is disabled. When OSCE = 1, changing the CLKIO output frequency does not change the frequency of the clock to the ADC and chargepump clock dividers. When OSCE = 0, the output of the CLKIO input dividers is applied to the ADC and chargepump clock dividers. The changes can take up to four CLKIO clock cycles due to internal synchronization. ADDIV<1:0>: ADC Clock Divider bits (default = 00). ADDIV<1:0> configures the ADC clock divider (see Table 19), and the output is the ADC master clock (Figure 3). If OSCE = 1, the input to the ADC clock divider is the output of the 3.6864MHz oscillator. If OSCE = 0 and CLKIO<1:0> 00, the output of the CLKIO input divider is applied to the input of the ADC clock divider. ACQCK<1:0> ADC Acquisition Clock bits (default = 01). ACQCK<1:0> set the number of ADC master clocks used for the ADC acquisition (see Table 20). For gains of 1 or 2 (GAIN<1:0> = 0X in the ADC Control register), the number of acquisition clocks can be set for 2, 4, 8, or 16. For gains of 4 or 8 (GAIN<1:0> = 1X), the number of acquisition clocks can be programmed to be 4, 8, 16, or 32.
NAME DEFAULT
MSB ODLY 0
OSCE 1
CLKIO1 1
CLKIO0 0
ADDIV1 0
ADDIV0 0
ACQCK1 0
LSB ACQCK0 1
Table 18. CLKIO Bit Configuration
CLKIO1 CLKIO0 CLKIO INPUT MODE (OSCE = 0) Input fCLKIO/4 fCLKIO/2 fCLKIO CLKIO OUTPUT MODE (MHz) (OSCE = 1) Disabled (output low) 1.2288 2.4567 4.9152
Table 19. ADC Clock Divider Bit Configuration
ADDIV1 0 0 1 1 ADDIV0 0 1 0 1 ADC CLOCK DIVIDER Divide by 1 Divide by 2 Divide by 4 Divide by 8
0 0 1 1
0 1 0 1
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CP/VM Control Register The CP/VM (Charge Pump/Voltage Monitor) Control register configures the interrupt polarity, charge-pump output voltage settings and power-down, supply voltage bypass switch state, and the voltage monitor settings for DVDD and AVDD. INTP: Interrupt Polarity bit (default = 0). INTP controls the output polarity for RST1 and RST2 when configured as interrupt outputs. INTP = 0 results in active-low operation and INTP = 1 selects active-high operation.
VM1<1:0>: Voltage Monitor 1 (VM1) Control bits (default = 00). VM1 monitors the voltage on DVDD. The VM1<1:0> bits control the threshold and output settings of VM1 (see Table 21). RST1 and RST2 are open-drain outputs when configured as voltage monitor outputs and are push-pull when configured as interrupt outputs. The VM1A status bit is set when DVDD drops below the 1.8V threshold and the VM1B status bit is set when DVDD drops below the 2.7V threshold. VM2CP<2:0>: Voltage Monitor 2 (VM2) and ChargePump Control bits (default = 000). VM2CP<2:0> control the charge pump, the bypass switch, and the AVDD voltage monitor. The charge pump generates a regulated AVDD supply voltage from a DVDD input. When activated (VM2CP = 100), the bypass switch internally shorts DVDD to AVDD. VM2 monitors the voltage on AVDD and sets the VM2 Status bit when AV DD drops below the threshold. CPDIV<1:0>: Charge-Pump Clock Divider bits (default = 00). The CPDIV<1:0> bits set the divider value for the input clock to the charge pump (see Table 23). If OSCE = 1, the input to the charge-pump clock divider is the 3.6864MHz oscillator output. If OSCE = 0 and CLKIO<1:0> 00, the output of the CLKIO input divider is applied to the input of the charge-pump clock divider. The charge pump is optimized to operate with a clock rate between 39kHz and 78kHz. Set the CPDIV<1:0> and CLKIO<1:0> bits to provide the optimal clock frequency for the charge pump.
LSB VM11 0 VM10 0 VM2CP2 0 VM2CP1 0 VM2CP0 0 CPDIV1 0 CPDIV0 0
MAX1329/MAX1330
MSB NAME DEFAULT INTP 0
Table 20. ADC Acquisition Clock Bit Configuration
ACQCK1 0 0 1 1 ACQCK0 0 1 0 1 ADC ACQUISITION CLOCKS GAIN = 1, 2 2 4 8 16 GAIN = 4, 8 4 8 16 32
Table 21. Voltage Monitor 1 Control Bit Configuration
VM11 0 0 1 1 VM10 0 1 0 1 RST1 OUTPUT 1.8V monitor 1.8V monitor Interrupt Interrupt RST2 OUTPUT 2.7V monitor Interrupt 2.7V monitor Interrupt VM1A STATE (1.8V MONITOR) On On Off Off VM1B STATE (2.7V MONITOR) On Off On Off
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Table 22. Voltage Monitor 2 and Charge-Pump Control Bit Configuration
VM2CP2 0 0 0 0 1 1 1 1 VM2CP1 0 0 1 1 0 0 1 1 VM2CP0 0 1 0 1 0 1 0 1 CHARGE-PUMP STATE Off On (3V) On (4V) On (5V) Off Off Off Off BYPASS SWITCH STATE Open Open Open Open Closed Open Open Open VM2 STATE (THRESHOLD VOLTAGE) Off On (2.7V) On (3.8V) On (4.5V) Off On (2.7V) On (3.6V) On (4.5V)
Table 23. Charge-Pump Clock Divider Bit Configuration
CPDIV1 0 0 1 1 CPDIV0 0 1 0 1 CHARGE-PUMP CLOCK DIVIDER Divide by 32 Divide by 64 Divide by 128 Divide by 256
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Switch Control Register The Switch Control register controls the two SPDT switches and the feedback switches for DACA, DACB, op amp 1, and op amp 2. The switches are controlled through the serial interface or by a configured DPIO. DSWA: DACA Switch Control bit (default = 0). The DSWA bit controls the state of the DACA switch. A logic-high in DSWA or on any DPIO_ configured as a DACA switch control input causes the DACA switch to close. The switch remains open when DSWA = 0 and all DPIO_ pins configured as DACA switch control inputs are logic-low. DPIO_ pins not configured as DACA switch control inputs are treated as logic zeros. See Table 24.
DSWB (MAX1329 only): DACB Switch Control bit (default = 0). A logic-high in DSWB or an any DPIO_ configured as a DACB switch control input causes the DACB switch to close. The switch remains open when DSWB = 0 and all DPIO_s configured as DACB switch control inputs are logic-low. DPIO_s not configured as DACB switch control inputs are treated as logic zeros. See Table 25.
MAX1329 NAME DEFAULT MAX1330 NAME DEFAULT MSB DSWA 0 X X OSW1 0 OSW2 0 SPDT11 0 SPDT10 0 SPDT21 0 LSB SPDT20 0 MSB DSWA 0 DSWB 0 OSW1 0 X X SPDT11 0 SPDT10 0 SPDT21 0 LSB SPDT20 0
OSW1: Op Amp 1 Switch Control bit (default = 0). The OSW1 bit and DPIO_ configured in OSW1 mode control the state of the op amp 1 switch. If DPIO_ is not configured for OSW1 mode, it is set to 0 as shown in Table 26. OSW2 (MAX1330 only): Op Amp 2 Switch Control bit (default = 0). The OSW2 bit and DPIO_ configured in OSW2 mode control the state of the op amp 2 switch. If DPIO_ is not configured for OSW2 mode, it is set to 0 as shown in Table 27. SPDT1<1:0>: Single-Pole, Double-Throw Switch 1 (SPDT1) Control bits (default = 00). The SPDT1<1:0> bits and DPIO_ configured for SPDT1 mode control the state of the switch. If DPIO_ is not configured for SPDT1 mode, it is set to 0 as shown in Table 28. SPDT2<1:0>: Single-Pole, Double-Throw Switch 2 (SPDT2) Control bits (default = 00). The SPDT2<1:0> bits and DPIO_ configured for SPDT2 mode control the state of the switch. If DPIO_ is not configured for SPDT2 mode, it is set to 0 as shown in Table 29.
MAX1329/MAX1330
X = Don't care.
Table 24. DACA Switch Control Configuration
DSWA BIT 0 X X X X 1 DPIO4 DPIO3 DPIO2 DPIO1 0 X X X 1 X 0 X X 1 X X 0 X 1 X X X 0 1 X X X X DACA SWITCH STATE (DSWA) Open Closed Closed Closed Closed Closed
Table 25. DACB Switch Control Configuration
DSWB BIT 0 X X X X 1 DPIO4 DPIO3 DPIO2 DPIO1 0 X X X 1 X 0 X X 1 X X 0 X 1 X X X 0 1 X X X X DACB SWITCH STATE (DSWB) Open Closed Closed Closed Closed Closed
X = Don't care.
X = Don't care.
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Table 26. Op Amp 1 Switch Control Configuration
OSW1 BIT 0 X X X X 1 DPIO4 DPIO3 DPIO2 DPIO1 0 X X X 1 X 0 X X 1 X X 0 X 1 X X X 0 1 X X X X OP AMP 1 SWITCH STATE (OSW1) Open Closed Closed Closed Closed Closed
Table 27. Op Amp 2 Switch Control Configuration
OSW2 BIT 0 X X X X 1 DPIO4 DPIO3 DPIO2 DPIO1 0 X X X 1 X 0 X X 1 X X 0 X 1 X X X 0 1 X X X X OP AMP 2 SWITCH STATE (OSW2) Open Closed Closed Closed Closed Closed
X = Don't care.
X = Don't care.
Table 28. SPDT1 Switch Control Configuration
SPDT11 BIT 0 0 0 0 0 0 1 1 1 1 1 1 SPDT10 BIT 0 X X X X 1 0 X X X X 1 DPIO4 0 X X X 1 X 0 X X X 1 X DPIO3 0 X X 1 X X 0 X X 1 X X DPIO2 0 X 1 X X X 0 X 1 X X X DPIO1 0 1 X X X X 0 1 X X X X SPDT1 SWITCH STATE SNO1-TO-SCM1 STATE Open Closed Closed Closed Closed Closed Open Closed Closed Closed Closed Closed SNC1-TO-SCM1 STATE Open Closed Closed Closed Closed Closed Closed Open Open Open Open Open
X = Don't care.
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Table 29. SPDT2 Switch Control Configuration
SPDT21 BIT 0 0 0 0 0 0 1 1 1 1 1 1 SPDT20 BIT 0 X X X X 1 0 X X X X 1 DPIO4 0 X X X 1 X 0 X X X 1 X DPIO3 0 X X 1 X X 0 X X 1 X X DPIO2 0 X 1 X X X 0 X 1 X X X DPIO1 0 1 X X X X 0 1 X X X X SPDT2 SWITCH STATE SNO2-TO-SCM2 STATE Open Closed Closed Closed Closed Closed Open Closed Closed Closed Closed Closed SNC2-TO-SCM2 STATE Open Closed Closed Closed Closed Closed Closed Open Open Open Open Open
APIO Control Register The Analog Programmable Input/Output (APIO) Control register configures the modes of APIO1-APIO4. APIO1-APIO4 I/O logic levels are referenced to AVDD and AGND (see Analog I/O in the Electrical Characteristics table). APIO_ is configurable as a general-purpose input,
MSB NAME DEFAULT AP4MD1 0 AP4MD0 0 AP3MD1 0
active-low wake-up input, general-purpose output, or serial-interface, level-shifted buffered I/O. AP_MD<1:0>: APIO_ Mode Configuration bits (default = 00). AP_MD<1:0> configures the APIO_ mode according to Table 30.
LSB AP3MD0 0 AP2MD1 0 AP2MD0 0 AP1MD1 0 AP1MD0 0
Table 30. APIO_ Mode Bit Configuration
AP_MD1 0 0 1 AP_MD0 0 1 0 MODE GPI WUL GPO DESCRIPTION Digital input. APIO_ logic level read from AP_LL register bit. Digital input. A falling edge on APIO_ sets the OSCE bit to 1 enabling the oscillator. Digital output. Set the APIO_ logic level by writing to the AP_LL register bit. Digital input or output. The SPI mode functions differ for each APIO1-APIO4. * APIO1 digital input. DOUT outputs the APIO1 logic level when CS is high, and APIO1 is a GPI, when CS is low. Set the resistor pullup configuration with the AP1PU bit. * APIO2 digital output. APIO2 outputs the DIN logic level when CS is high and becomes a GPO with the level set by AP2LL bit when CS is low. * APIO3 digital output. APIO3 outputs the SCLK logic level when CS is high and becomes a GPO with the level set by the AP3LL bit when CS is low. * APIO4 digital output. APIO4 inverts and then outputs the CS logic level.
1
1
SPI
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
APIO Setup Register The APIO Setup register programs the resistor pullup and the logic level for APIO1-APIO4.
AP<4:1>PU: APIO Resistor Pullup bits (default = 1111). AP_PU controls the internal 500k (typ) pullup resistor on the corresponding APIO_. AP_PU = 0 disables the pullup resistor and AP_PU = 1 connects the pullup resistor to AVDD. The pullup resistor is active only when the corresponding APIO_ is configured as an input. AP<4:1>LL: APIO Logic-Level bits (default = 0000). If APIO_ is programmed as a GPO, set the corresponding AP_LL = 0 to set APIO_ to a logic-low level or set AP_LL = 1 to set APIO_ to a logic-high level. A read from AP_LL returns the logic level at the corresponding APIO_ when the register is read, regardless of the APIO mode.
MSB NAME DEFAULT AP4PU 1 AP3PU 1 AP2PU 1 AP1PU 1 AP4LL 0 AP3LL 0 AP2LL 0 LSB AP1LL 0
DPIO Control Register The Digital Programmable Input/Output (DPIO) Control register programs the modes of the DPIO1-DPIO4. DPIO1-DPIO4 are referenced to DVDD and DGND (see Digital I/O in the Electrical Characteristics table). DP_MD<3:0>: DPIO_ Mode Configuration bits (default = 0000). DP_MD<3:0> configures the corresponding DPIO_ (see Table 31).
MSB NAME DEFAULT NAME DEFAULT DP4MD3 0 DP2MD3 0 DP4MD2 0 DP2MD2 0 DP4MD1 0 DP2MD1 0 DP4MD0 0 DP2MD0 0 DP3MD3 0 DP1MD3 0 DP3MD2 0 DP1MD2 0 DP3MD1 0 DP1MD1 0 DP3MD0 0 LSB DP1MD0 0
DPIO Setup Register The DPIO Setup register configures the pullup resistor and logic level on DPIO1-DPIO4. DP<4:1>PU: DPIO Resistor Pullup bits (default = 1111). DP_PU controls the internal 500k (typ) pullup resistor on the corresponding DPIO_. DP_PU = 0 disables the pullup resistor and DP_PU = 1 connects the pullup resistor to DVDD. The pullup resistor is active only when the corresponding DPIO_ is configured as an input.
DP<4:1>LL: DPIO Logic-Level bits (default = 0000). If DPIO_ is programmed as a GPO, set the corresponding DP_LL = 0 to set DPIO_ to a logic-low level or set DP_LL = 1 to set DPIO_ to a logic-high level. A read from DP_LL returns the logic level at the corresponding DPIO_ when the register is read, regardless of the DPIO mode.
LSB DP1LL 0
NAME DEFAULT
MSB DP4PU 1
DP3PU 1
DP2PU 1
DP1PU 1
DP4LL 0
DP3LL 0
DP2LL 0
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Table 31. DPIO_ Mode Bit Configuration
DP_MD3 DP_MD2 DP_MD1 DP_MD0 0 0 0 0 0 0 0 0 1 0 1 0 MODE MAX1329 GPI WUL WUH MAX1330 GPI WUL WUH DESCRIPTION Digital input. DPIO_ logic-level read from DP_LL register bit. Digital input. A falling edge on WUL sets the OSCE bit enabling the oscillator. Digital input. A rising edge on WUH sets the OSCE bit enabling the oscillator. Digital input. A logic-low on SLP overrides the register settings and powers down all circuits except VM1 and all the registers. A logichigh on SLP transfers the power control back to the register settings. See the Clock Control Register section. Digital input. A logic-low on SHDN overrides the register settings and powers down all circuits. A logic-high on SHDN transfers the power control back to the register settings. Digital input. A rising edge on DLAB shifts DACA and DACB data from the input register to the output register or sequences through FIFOA if enabled. For the MAX1330, this applies only to DACA. Digital input. CONVST controls acquisition time and conversion start. A falling edge on CONVST puts the ADC in acquisition mode. A rising edge on CONVST starts a single conversion. Digital input. A rising edge on DLDA shifts DACA data from the input to output register or sequences through FIFOA if enabled. Digital input. DSWA and OSW3 control the DACA and op amp 3 switches, respectively. See the Switch Control Register section. Digital input. A rising edge on DLDB shifts DACB data from the input to output register. Digital input. DACB and op amp 2 control the DACB and op amp 2 switches, respectively. See the Switch Control Register section. Digital input. Op amp 1 switch control. See the Switch Control Register section. Digital input. SPDT1 controls the SPDT1 switch. See the Switch Control Register section.
0
0
1
1
SLP
SLP
0
1
0
0
SHDN
SHDN
0
1
0
1
DLAB
DLAB
0
1
1
0
CONVST
CONVST
0 1 1
1 0 0
1 0 0
1 0 1
DLDA DSWA DLDB
DLDA DSWA --
1
0
1
0
DSWB
OSW2
1 1
0 1
1 0
1 0
OSW1 SPDT1
OSW1 SPDT1
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Table 31. DPIO_ Mode Bit Configuration (continued)
DP_MD3 DP_MD2 DP_MD1 DP_MD0 1 1 0 1 MODE MAX1329 SPDT2 MAX1330 SPDT2 DESCRIPTION Digital input. SPDT2 controls the SPDT2 switch. See the Switch Control Register section. Digital output. DRDY goes high when a conversion is complete and valid ADC data is available in the ADC Data register. If the ADC Data or Status register is read, DRDY returns low. If high, DRDY pulses low for one ADC master clock cycle while updating the ADC Data register before returning high. Digital output. Write to the DP_LL register bits to set the GPO level.
1
1
1
0
DRDY
DRDY
1
1
1
1
GPO
GPO
Status Register The Status register is a 24-bit register that contains Status bits from all blocks. Setting a Status bit causes the interrupt output to assert when the corresponding Interrupt Mask bit in the Interrupt Mask register is cleared. If a Status bit is set and an event occurs to set it again, the Status bit and interrupt output remain asserted. All Status bits clear once the Status register has been read successfully. Updating of the Status register is delayed during a read until the Status register read has been completed.
VM1A: 1.8V DVDD Voltage-Monitor Status bit (default = 0). VM1A indicates the status of the 1.8V DVDD voltage monitor. The VM1A = 1 when the DVDD voltage drops below the 1.8V threshold. The VM1A bit clears to 0 when the Status register is read and only if the condition is no longer true. When the 1.8V DVDD voltage monitor is powered down, the previous state of the bit is maintained until it is read and it cannot be set to 1 in this state. Note: The default state is 0. However, at power-up, the voltage monitor asserts VM1A. Read the Status register after power-up to reset VM1A to 0. VM1B: 2.7V DVDD Voltage-Monitor Status bit (default = 0). VM1B indicates the status of the 2.7V DVDD voltage monitor. VM1B = 1 when the DVDD voltage drops below the 2.7V threshold. The VM1B bit clears to 0 when the Status register is read and only if the condition is no longer true. When the 2.7V DVDD voltage monitor is powered down, the previous state of the bit is maintained until it is read and it cannot be set to 1 in this state. Note: The default state is 0. However, at power-up, the voltage monitor asserts VM1B. Read the Status register after power-up to reset VM1B to 0.
VM2: AVDD Voltage-Monitor Status bit (default = 0). VM2 indicates the status of the AVDD voltage monitor. VM2 = 1 when the AV DD voltage drops below the threshold programmed by the VM2CP<2:0> bits. VM2 clears to 0 when the Status register is read and only if the condition is no longer true. When the AVDD voltage monitor is powered down, the previous state of the bit is maintained until it is read and it cannot be set to 1 in this state. ADD: ADC Done Status bit (default = 0). The ADD bit indicates when an ADC conversion has completed and the data is ready to be read from the ADC Data register. ADD is set to 1 after the data from an ADC conversion has been written to the ADC Data register. ADD clears to 0 when the Status register or the ADC Data register is read. AFF: ADC FIFO Full Status bit (default = 0). The AFF bit indicates that the ADC has written data to the ADC FIFO address programmed by the AFFI<3:0> bits. The AFF bit is set to 1 when the address has been written. AFF clears to 0 when the Status register is read or when the ADC FIFO register is read (any number of ADC data words) or written. ACF: ADC Accumulator Full Status bit (default = 0). The ACF bit indicates that the programmed number of ADC conversion results have been accumulated. The result is saved in the ACCDATA<19:0> bits in the ADC Accumulator register for the next programmed number of accumulations before it is overwritten. The ACF bit sets to 1 when the ADC Accumulator is filled to the programmed address. The ACF bit clears to 0 when the Status register is read or when the ADC Accumulator register is read or written.
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NAME DEFAULT MSB VM1A 0* VM1B 0* VM2 0 ADD 0 AFF 0 ACF 0 GTA 0 LTA 0
NAME DEFAULT
APR4 0
APR3 0
APR2 0
APR1 0
APF4 0
APF3 0
APF2 0
APF1 0 LSB DPF1 0
NAME DEFAULT
DPR4 0
DPR3 0
DPR2 0
DPR1 0
DPF4 0
DPF3 0
DPF2 0
*The default states for VM1A and VM1B are 0. However, at power-up, the voltage monitor asserts VM1A and VM1B.
GTA: ADC Greater-Than (GT) Alarm Status bit (default = 0). GTA = 1 indicates that ADC GT alarm has been tripped. The GTA bit clears to 0 by reading the Status register or by writing the ADC GT Alarm register. LTA: ADC Less-Than (LT) Alarm Status bit (default = 0). LTA = 1 indicates that the ADC LT alarm has been tripped. The LTA bit clears to 0 by reading the Status register or by writing the ADC LT Alarm register. APR<4:1>: APIO Rising-Edge Status bit (default = 0). A logic-high in the APR<4:1> bits indicate that a rising edge has been detected on the corresponding APIO_. APR_ clears to 0 when the Status register is read.
APF<4:1>: APIO Falling-Edge Status bit (default = 0). A logic-high in the APF<4:1> bits indicate that a falling edge has been detected on the corresponding APIO_. APF_ clears to 0 when the Status register is read. DPR<4:1>: DPIO Rising-Edge Status bit (default = 0). A logic-high in the DPR<4:1> bits indicate that a rising edge has been detected on the corresponding DPIO_. DPR_ clears to 0 when the Status register is read. DPF<4:1>: DPIO Falling-Edge Status bit (default = 0). A logic-high in the DPF<4:1> bits indicate that a falling edge has been detected on the corresponding DPIO_. DPF_ clears to 0 when the Status register is read.
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
Interrupt Mask Register The Interrupt Mask register bits enable the Status bits to generate an interrupt on RST1 and/or RST2 if programmed as interrupts (configured by VM1<1:0> in the CP/VM Control register). Clearing a mask bit to 0 enables the corresponding bit in the Status register to generate an interrupt. Setting a mask bit to 1 prevents the Status bit from generating an interrupt. If the interrupt output is asserted and another interrupt occurs, the interrupt output remains asserted. Interrupt conditions on RST1 and/or RST2 are released after recognizing a read to the Status register. Updating of the Status register is delayed until after the Status register has been read. If the Status register read was aborted or if a new unmasked Status bit is set during the read, the interrupt output reasserts at the end of the read (see Figure 15). MV1A: 1.8V DVDD Voltage-Monitor Mask bit (default = 1). Set MV1A = 0 to unmask the VM1A Status bit to generate an interrupt. MV1B: 2.7V DVDD Voltage-Monitor Mask bit (default = 1). Set MV1B = 0 to unmask the VM1B Status bit to generate an interrupt. MVM2: AVDD Voltage-Monitor Mask bit (default = 1). Set MVM2 = 0 to unmask the VM2 Status bit to generate an interrupt. MADD: ADC Done Mask bit (default = 1). Set MADD = 0 to unmask the ADD Status bit to generate an interrupt.
MAX1329/MAX1330
MAFF: ADC FIFO Full Mask bit (default = 1). Set MAFF = 0 to unmask the AFF Status bit to generate an interrupt. MACF: ADC Accumulator Full Mask bit (default = 1). Set MACF = 0 to unmask the MACF Status bit to generate an interrupt. MGTA: ADC GT Alarm Mask bit (default = 1). Set MGTA = 0 to unmask the GTA Status bit to generate an interrupt. MLTA: ADC LT Alarm Mask bit (default = 1). Set MLTA = 0 to unmask the LTA Status bit to generate an interrupt. MAPR<4:1>: APIO Rising-Edge Mask bits (default = 1111). Set MAPR_ = 0 to unmask the corresponding APIO_ Status bit to generate an interrupt. MAPF<4:1>: APIO Falling-Edge Mask bits (default = 1111). Set MAPF_ = 0 to unmask the corresponding APIO_ Status bit to generate an interrupt. MDPR<4:1>: DPIO Rising-Edge Mask bits (default = 1111). Set MDPR_ = 0 to unmask the corresponding DPIO_ Status bit to generate an interrupt. MDPF<4:1>: DPIO Falling-Edge Mask bits (default = 1111). Set MDPF_ = 0 to unmask the corresponding DPIO_ Status bit to generate an interrupt.
Reset Register A write to the Reset register resets all registers to their default values. A valid write consists of the 8-bit address and 8 don't-care bits of data. The reset occurs on the 16th rising edge of SCLK.
NAME DEFAULT
MSB MV1A 1
MV1B 1
MVM2 1
MADD 1
MAFF 1
MACF 1
MGTA 1
MLTA 1
NAME DEFAULT
MAPR4 1
MAPR3 1
MAPR2 1
MAPR1 1
MAPF4 1
MAPF3 1
MAPF2 1
MAPF1 1 LSB MDPF1 1
NAME DEFAULT
MDPR4 1
MDPR3 1
MDPR2 1
MDPR1 1
MDPF4 1
MDPF3 1
MDPF2 1
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POWER SUPPLY 0.1F 2.7V TO 3.6V POWER SUPPLY 0.1F 0.1F CDVDD 2.7V TO 3.6V 5.0V CFLY CAVDD 0.1F
DVDD
C1A
C1B
AVDD
VDD
DVDD
C1A
C1B
AVDD
VDD
MAX1329 MAX1330
RST1 RST2
INTERRUPT C RESET
MAX1329 MAX1330
RST1 RST2
INTERRUPT C RESET
DGND
AGND
DGND
DGND
AGND
DGND
Figure 23. Power-Supply Circuit Using an External 3.0V Power Supply for DVDD and AVDD
Figure 24. Power-Supply Circuit Using an External 3.0V Power Supply for DVDD and Internal Charge Pump Set to 5V for AVDD
1.8V TO 3.6V 3.0V CDVDD E1 DVDD C1A C1B AVDD VDD CFLY CAVDD 0.1F
Applications Information
Power-Supply Considerations
The circuit in Figure 23 applies an external 3.0V power supply to both DVDD and AVDD. To drive AVDD directly, disable the internal charge pump through the CP/VM Control register. The bypass switch between DVDD and AVDD can be either open or closed in this configuration. Figure 24 shows the charge pump enabled to supply AVDD. The charge-pump output voltage is set to 5.0V through the CP/VM Control register. See the ChargePump Component Selection section. Figure 25 shows DVDD is powered from a battery with the charge-pump output set to 3.0V. The charge pump can draw high peak currents from DVDD under maximum load. Select an appropriately sized bypass capacitor for DVDD ( 10 times CFLY). Supply ripple can be reduced by increasing CAVDD and/or the charge-pump clock frequency.
MAX1329 MAX1330
RST1 RST2
RESET C INTERRUPT
DGND
AGND
DGND
Figure 25. Power-Supply Circuit Using a Battery for DVDD and Internal Charge Pump Set to 3.0V for AVDD
Digital-Interface Connections
Figure 26 provides standard digital-interface connections between the MAX1329/MAX1330 and a C. The C generates its own 32kHz clock for timekeeping and the MAX1329/MAX1330 provide the high-frequency clock required by the C. See the Clock Control Register section to program the CLKIO output and frequency and set the ODLY bit to delay the turn-off time to enable the C time to go to sleep. During sleep, CLKIO becomes an input and requires a weak pulldown resistor (1M) to minimize power dissipation. See the DPIO Setup and DPIO Control registers to program DPIO1-DPIO4 as wake-ups. Upon wake-up, the internal oscillator starts and outputs to CLKIO. See the CP/VM Control Register section to program the RST1 and RST2 as a reset or interrupt.
63
Running Directly Off Batteries
The MAX1329/MAX1330 can be powered directly from two alkaline cells, two silver oxide button cells, or a lithium-coin cell. DVDD requires 1.8V to 3.6V and AVDD requires 2.7V to 5.5V for proper operation. Save power by running DVDD directly off the battery and shorting to AVDD by closing the internal bypass switch. Use the 2.7V AVDD voltage monitor to detect when it drops to 2.7V. Power is saved during this time because the internal charge pump is off. Once the battery voltage drops to 2.7V, open the bypass switch and enable the internal charge pump as long as DVDD is between 1.8V and 2.7V. Following this procedure optimizes the battery life.
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Communication with a Peripheral Device Powered by the MAX1329/MAX1330
The circuit in Figure 27 shows the MAX1329/MAX1330 providing an interface between a C and a peripheral device powered by different supply voltages. This eliminates the need for external level-translation circuitry due to the different supply voltages. The internal charge pump boosts the C supply voltage (DVDD) to the peripheral device supply voltage (AVDD). See the APIO Control and APIO Setup registers to program APIO2-APIO4 as DIN, SCLK, and CS outputs to the peripheral device, respectively, and APIO1 as the DOUT input from the peripheral device. The digital inputs at DIN, SCLK, and CS are level-translated from DVDD to AVDD and output at the configured APIO2, APIO3, and APIO4 outputs. The digital output at DOUT is level-translated from AVDD to DVDD from the configured APIO1 input.
32.768kHz XIN
MAX1329 MAX1330
CLKIO CS SCLK DIN DOUT
XOUT C HCLKIN OUTPUT SCK MOSI MISO
RST1 RST2 DPIO1 DPIO2
RESET INTERRUPT
INTERRUPT INTERRUPT
Figure 26. Digital-Interface Connections
3.0V/4.0V/5.0V POWER SUPPLY EXTERNAL 1.8V TO 3.6V CFLY CDVDD DVDD DVDD C1A C1B AVDD CAVDD
AVDD
OUTPUT C SCK MOSI MISO DGND
CS SCLK DIN
MAX1329 MAX1330
APIO4 APIO3 APIO2
CS
PERIPHERAL DEVICE
SCLK DIN
DOUT DGND AGND
APIO1
DOUT AGND
Figure 27. Communication with a Peripheral Device Powered by the MAX1329/MAX1330
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
REFDAC
OUTA DACA DSWA
FBA LED SNO1 SCM1 SNC1
VBAT
SPDT1
Q1
MAX1329 SNC2 SCM2 SNO2 REFDAC
VBAT LED
SPDT2
Q2
RB OUTB DACB DSWB IF RF
FBB PHOTO DIODE AV = 0.5, 0.82, 1 2.5V REF REFDAC AV = 0.5, 0.82, 1 2.50V REFADC REFADJ 0.01F 1F 1.25V 1F
Figure 28. Optical Reflectometry Application with Dual LED and Single Photodiode
Optical Reflectometry Application with Dual LED and Single Photodiode
Figure 28 illustrates the MAX1329 in an optical reflectometry application with two transmitting LEDs and one receiving photodiode. The LEDs transmit light at specific frequencies onto the sample strip and the photodiode receives the reflections from the strip. Set the DACA output to provide the appropriate bias currents for the LEDs.
The DSWA and DSWB switches are open in this configuration. The LED bias current is calculated as ILED = VOUTA/RB. REFADC is used as an analog ground and DACB is set to ensure that the photodiode is not forward biased. The IF current is converted to a voltage through the R F resistor and measured by the internal ADC. SPDT1 and SPDT2 are configured as single-pole double-throw switches and enable switching between
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
the two LEDs. The LEDs can be powered directly from VBAT or from AVDD powered by the internal charge pump if the VD of the LEDs require a higher or regulated voltage. Ambient light rejection is performed in the digital domain in this configuration by digitizing the photodiode current with the internal ADC while both LEDs are off and subtracting this from the result when the LEDs are turned on.
Two-Electrode Potentiostat with AC and DC Excitation
The circuit in Figure 30 shows the MAX1330 in a twoelectrode potentiostat application with both AC and DC excitation to the sensor. The DSWA can be open or closed and OSW1 and OSW2 should be normally open although OSW1 can be closed during high sensor current to keep op amp 1 in compliance. REFADC is analog ground and the working electrode (WE) is connected to analog ground through op amp 1. The sensor current to be measured is converted to a voltage through RF and measured by the internal ADC. For DC operation, the bias voltage between WE and the counter electrode (CE) is set by DACA. For AC operation, DACA is configured to generate a waveform by programming the FIFOA Control and FIFOA Data registers for the desired operation. Op amp 2 is configured as a 2nd-order Sallen Key lowpass filter to smooth the steps in the AC waveform going to the sensor. The DACA can be sequenced to create an AC waveform through the SPI interface or by configuring one of the DPIOs and driving it with a clock. The internal ADC includes a 16-word FIFO to facilitate data gathering during this mode of operation.
Three-Electrode Potentiostat with Software-Switchable Single- or DualChannel Connection
The MAX1329 is used in a software switchable singleor dual-channel three-electrode potentiostat application (see Figure 29). In both configurations, the DAC buffer feedback switches, DSWA and DSWB, are normally open but can be closed during high sensor current to keep the DAC buffer outputs compliant. In the dualchannel configuration, the SPDT1 switch is open and the OSW1 switch is closed. DACA biases the working electrode (WE) and DACB biases the reference electrode (RE) both relative to the counter electrode (CE). The CE is shared by the two channels. In this configuration, RE is really a second working electrode and IA and IB are the two sensor currents being measured. IA and IB are converted to voltages through RA and RB and measured by the internal ADC. In the single-channel configuration, the SPDT1 switch is closed and the OSW1 switch is open. DACA biases the WE relative to the RE and the RE is set by IN1-. Op amp 1's forcesense configuration holds RE constant while the CE swings up and down depending on the sensor current and the sensor impedance. In this configuration, IA is the sensor current being measured. The R1 resistor is typically a large value to keep op amp 1 stable when the sensor is not present or not active.
Temperature Measurement with Two Remote Sensors
For external measurements, select single-ended AIN1 and AIN2 temperature measurement relative to AGND in the lower multiplexer. Two diode-connected 2N3904 transistors are used as external temperature sensing diodes in Figure 31. For internal temperature sensor measurements, select internal temperature measurement in the lower multiplexer. During all temperature measurements, autoconvert and burst modes are unavailable. Divide the ADC result by eight to obtain the measured temperature. When using an external reference at REFADJ, disable the internal reference and use the temperature correction equation in the Temperature Measurement section.
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
MAX1329 REFDAC
OUTA DACA DSWA IA RA
REFDAC
FBA
OUTB DACB DSWB IB RB WE
FBB SNO1 SCM1 SNC1 IN1OSW1 OA1 OUT1 IN1+
RE CE
SPDT1
R1
1.25V AV = 0.5, 0.82, 1 2.5V REF REFDAC AV = 0.5, 0.82, 1 2.50V REFADC REFADJ 0.01F 1F 1F
Figure 29. Three-Electrode Potentiostat Software-Switchable Single- or Dual-Channel Connection
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
MAX1330 IN1OSW1 OA1 OUT1
RF
IN1+ 1.25V AV = 0.5, 0.82, 1 2.5V REF REFADC REFADJ CE REFDAC AV = 0.5, 0.82, 1 2.50V 0.1F SENSOR 1F IN2R3 1F WE
OSW2 OA2 OUT2
C1 IN2+ C2 REFDAC R1 R2
OUTA DACA DSWA
FBA
Figure 30. Two-Electrode Potentiostat with AC and DC Excitation
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
AIN1 CAIN1* AGND 2N3904 AIN1 AIN2 OUTA/OUT3 FBA/IN3OUT1 IN1OUTB/OUT2 FBB/IN2TEMP1 TEMP2 TEMP3 DVDD/4 AVDD/4 REFADC REFDAC AGND AV = 0.5, 0.82, 1 MAX1329 MAX1330 TEMP SENSOR 2.5V REF AV = 0.5, 0.82, 1 REFADC REFADJ REFDAC 0.01F 1F MUX PGA AV = 1, 2, 4, 8 12-BIT ADC REFADC
DITHER ACCUMULATOR ALARM MUX ADC FIFO
AIN2 CAIN2* AGND 2N3904
1F
TEMP1
*FOR BEST RESULTS, LIMIT CAIN1 AND CAIN2 TO 10pF.
Figure 31. Temperature Measurement with Two Remote Sensors
Programmable-Gain Instrumentation Amplifier
Two op amps and two SPDT switches are configured as a programmable-gain instrumentation amplifier in Figure 32. It includes a differential input and a singleended output. SPDT1 and SPDT2 are configured as single-pole, double-throw switches. The gain is set by the following equations: R + R3 VOUT = 2 + 1 (VIN+ - VIN- ) R1 for switch position 1, and R3 VOUT = + 1 (VIN+ - VIN- ) R1 + R2 for switch position 2.
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
IN1+ OA1 IN1R3 OSW1 SCM1 SPDT1 IN2+ OA2 IN2R1 OSW2 SCM2 SPDT2 SNC2 R3 SNO2 OUT2 SNC1 R1 SNO1 R2 OUT1 VOUT
VIN+
VIN-
R2
MAX1330
Figure 32. Programmable-Gain Instrumentation Amplifier, Switch Position 1
Round the FIFOA_DATA(n) values to the nearest integer and write these values to the FIFOA Data register. Figure 33 shows a sine wave with a 2VP-P output and with a 1.25V offset. Write the DAC Control register with 0x43 to enable DACA, enable the internal reference, and to set REFDAC to 2.5V. Write to the DACA input and output register by performing a direct mode write with 0x4800 to set DACA to midscale or 1.25V. Write the FIFOA Control register with 0x7F to disable FIFOA and allow a write to the FIFOA Data register, enabling bipolar, symmetry, and continuous modes, and setting the depth to 16. The FIFOA data calculated from the above equation is 161, 320, 476, 627, 772, 910, 1039, 1159, 1267, 1362, 1445, 1514, 1568, 1607, 1631, and 1638 decimal. Write the FIFOA Data register with 0x0A10 1400 1DC0 2730 3040 38E0 40F0 4870 4F30 5520 5A50 5EA0 6200 6470 65F0 6660 as a contiguous bit stream to fill the FIFOA Data register with data. Write to the FIFOA Control register with 0xFF to enable FIFOA and to disallow writes to the FIFOA Data register. Write to the DPIO Control register with 0x0007 to program DPIO1 as an input to sequence the DACA FIFO on each rising edge. Write to the Switch Control register with 0x80 to close the DACA switch to put the buffer into unity gain. Input a continuous clock to DPIO1 that is 4 x N times (N = 16) the desired frequency of the synthesized waveform. Figure 33 should be observable on OUTA.
MAX1329/MAX1330
Synthesizing a Sine Wave
The MAX1329/MAX1330 can easily create up to a 64-point single or periodic sine wave using the DACA and FIFOA. The 16-word FIFO or memory is used to create the first quarter of the waveform and symmetry is used to extend the waveform to produce a complete period. See the DAC FIFO and Direct Digital Synthesis (DDS) Logic section for detailed waveform generation. The first data point is the DACA input register data. The FIFOA data is offset from this initial data. To determine the values to be written to the FIFOA Data register use the following equation. FIFOA_DATA(n) = A x sin((n/N) x 90) where n = 1 to N, N = DPTA<3:0>, A = (VPEAK/VREFDAC) x 4096, VPEAK is the desired peak voltage of the sine wave, and V REFDAC is the DAC reference voltage programmed at REFDAC.
2.50 2.25 2.00 DAC OUTPUT (V) 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 0 10 20
SINE WAVE
30
40
50
60
70
DAC SEQUENCES
Figure 33. Example Sine-Wave Output
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
Charge-Pump Component Selection
Optimize the charge-pump circuit for size, quiescent current, and output ripple by properly selecting the operating frequency and capacitors CDVDD, CFLY, and CAVDD (Table 32). The charge pump is capable of providing a maximum of 25mA including what is used internally. If less than 25mA is required, smaller capacitor values can be utilized. For lowest ripple, select 117kHz operation (CPDIV<1:0> = 00 and OSCE = 1 when using the internal oscillator). In addition, increasing C AVDD relative to C FLY further reduces ripple. For highest efficiency, select 14.6kHz operation (CPDIV<1:0> = 11 and OSCE = 1 when using the internal oscillator) and select the largest practical values for CAVDD and CFLY while maintaining at least a 30-to-1 ratio. For smallest size, select 117kHz operation. See Table 32 for some suggested values and resulting ripple for 25mA load current. See Figure 34 for load current vs. flying capacitor value when optimizing for other load currents. Note that the capacitors must have low ESR to maintain low ripple. The CFLY flying capacitor ESR needs to be < 0.1; and the CAVDD and CDVDD filter capacitor ESR needs to be < 0.3. The CFLY flying capacitor can easily be a ceramic capacitor; and the CAVDD and CDVDD filter capacitor can be a low-ESR tantalum or may need to be a combination of a small ceramic and a larger tantalum capacitor. When DVDD is lower than AVDD, the charge pump always operates in voltage-doubler mode. It regulates the output voltage using a pulse-width-modulation (PWM) scheme. Using a PWM scheme ensures that the charge pump is synchronous with the internal ADC preventing corruption of the conversion results.
Operating the Analog Switches
The MAX1329/MAX1330 include two single-pole doublethrow (SPDT) and three single-pole single-throw (SPST) analog switches. The two SPDT analog switches are uncommitted and the three SPST analog switches are connected between the DAC buffer or op amp outputs and the inverting inputs. The analog switches can be controlled using the Switch Control register or any of the DPIOs. See the DPIO Control and DPIO Setup registers to program the DPIOs. The DPIOs should be used when direct control is critical such as synchronizing with another event or if the SPI bus bandwidth is not sufficient for the intended application. The register bit for the analog switch is logically OR'd with DPIOs enabled to control that switch. The SPDT1 and SPDT2 analog switches can be operated as a SPDT or as a double-pole single-throw (DPST). In the DPST mode, both switches can be opened or closed together. This is useful when connecting two external nodes to a common point. If a lower on-resistance is required, NO_ and NC_ can be connected together externally and be used as a SPST analog switch with half the on-resistance. The SPST analog switches are intended to be used to set the DAC buffers and op amps to unity gain internally by software control. When the DAC buffers and op amps are used as transimpedance amplifiers, the SPST analog switches can be used to short the external transimpedance resistor during high current periods to keep the amplifier output in compliance.
MAX1329/MAX1330
Table 32. External Component Selection for 25mA Output Current and 2VDVDD VAVDD 0.4V (Figure 25)
MAX
ILOAD (mA)
CHARGE-PUMP LOAD CURRENT vs. FLYING CAPACITOR VALUE
45 40 35 fCP = 115.2kHz fCP = 57.6kHz
MAX1329 fig34
50
CHARGE-PUMP CLOCK (kHz) 14.4 28.8 57.6 115.2
ILOAD, (mA) 25 12.5 25 12.5 25 12.5 25 12.5
CFLY (F) 1.7 0.9 0.9 0.4 0.4 0.2 0.2 0.1
CAVDD CDVDD RIPPLE (F) (F) (mV) 55.6 27.8 27.8 13.9 13.9 6.9 6.9 3.5 17.4 8.7 8.7 4.3 4.3 2.2 2.2 1.1 32 32 32 32
30 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CFLY (F) fCP = 14.4kHz fCP = 28.8kHz
Figure 34. Load Current vs. CFLY Value for 2VDVDD - VAVDD 0.4V
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Using the Internal Reference and Reference Buffers
The MAX1329/MAX1330 include a precision 2.5V internal reference and two independent programmable buffers for the ADC and DACs. See the ADC Control and DAC Control registers to enable the internal reference and program the buffers. The REFADJ output is fixed at 2.5V (REFE = 1) and the REFADC and REFDAC connect to the internal ADC reference input and the internal DAC reference inputs, respectively. These buffers can be programmed to output 1.25V, 2.048V, or 2.5V independent of each other. This allows the dynamic range of the ADC and DACs to be optimized or set differently. This is useful if one of the reference voltages is needed to be approximately AVDD/2 to be used as an analog ground. The flexibility of the reference circuit allows the internal reference to be shutdown (REFE = 0) and an external voltage reference applied to REFADJ. If either REFADC or REFDAC requires a different or more accurate voltage, an external reference can be applied directly to REFADC or REFDAC and the corresponding reference buffer must be disabled.
0 -5 -10 FILTER RESPONSE (dB) -15 -20 -25 -30 -35 -40 -45 -50 0 60 120 180 240 300 360 420 480 FREQUENCY (Hz)
DIGITAL-FILTER TRANSFER FUNCTION
Figure 35. Plot of the Digital Filter with 60Hz Notch
Applying a Digital Filter to ADC Data Using the 20-Bit Accumulator
The MAX1329/MAX1330 incorporate a 20-bit accumulator that can sum up to 256 results of the 12-bit ADC automatically. See the ADC Accumulator Register section to set the number of samples to be summed. Once the accumulator is full, the ACF bit in the Status register is asserted. The accumulator provides a digital filtering sync function, with an effective data rate equal to fEDR = fS/n where fS is the ADC sample rate and n is the number of samples accumulated. There is a notch at every integer multiple of fEDR. The following equation provides the transfer function of the filter: nf sin nf fs H(f) = = sinc nf fs f s
Figure 35 is a plot showing a notch at 60Hz by accumulating 256 samples at 15.36ksps. The final step is to read the data in the ADC Accumulator register and divide by the number of samples that were accumulated. Shift the data right for each binary multiple of accumulated data. For example, for 256 samples the data should be shifted right eight times.
Increasing ADC Resolution using the Accumulator with Dither
The MAX1329/MAX1330 incorporate an internal dither function that can be used along with the 20-bit accumulator to easily increase the resolution of the 12-bit ADC to up to 16 bits. The oversampling along with the dither increases the resolution with the penalty of a lower effective data rate. Use the following equation to determine the number of samples required to increase the resolution by N number of bits: Samples = 22N To increase the resolution by 4 bits, from 12 to 16 bits, 256 samples are required. After accumulating the required number of samples, read the data from the ADC Accumulator register and shift right by 4 bits with the 16 LSBs as the increased resolution result.
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
Using the ADC with the ADC LT (Less-Than) and GT (Greater-Than) Digital Alarms
The ADC LT and GT alarms compare the latest ADC result to the values programmed in the ADC LT Alarm and ADC GT Alarm registers, if enabled, and assert the appropriate GTA or LTA status bit in the Status register once the threshold has been exceeded. The digital alarms can be used as a safeguard during normal ADC conversions to signify an event. Change the GT and LT alarm thresholds, if needed, when selecting a new mux input channel. The ADC can be put into autoconversion mode to continuously convert without user intervention. See the AUTO<2:0> bits in the ADC Control Register section to enable the auto mode and to program the ADC conversion rate.
Layout, Grounding, and Bypassing
For best performance, use PCBs. Do not use wire-wrap boards. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) signals parallel to one another or run digital lines underneath the MAX1329/MAX1330 package. High-frequency noise in the VDD power supply can affect the MAX1329/MAX1330 performance. Bypass the AVDD and DVDD supplies with a 0.1F capacitor to GND, close to the AVDD and DVDD pins (see Table 32 for recommended capacitor values). Minimize capacitor lead lengths for best supply-noise rejection.
MAX1329/MAX1330
Selector Guide
PART NO. OF DACS NO. OF OP AMPS TEMP SENSOR ACCURACY (C) 3 3 INTERNAL REFERENCE TEMP COEFFICIENT (ppm/C max) 75 75 TEMP RANGE -40C to +85C -40C to +85C
MAX1329BETL+ MAX1330BETL+
2 1
1 2
+Denotes a lead-free/RoHS-compliant package.
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Functional Diagrams
DVDD CLKIO RST1 RST2 C1A C1B AVDD
CS SCLK DIN DOUT SERIAL I/O
INTERNAL CLOCK AND DIVIDER
VOLTAGE SUPERVISORS AND INTERRUPTS
CHARGE PUMP DPIO
DPIO1 DPIO2 DPIO3
AIN1 AIN2 OUTA FBA OUT1 IN1OUTB FBB TEMP SENSOR TEMP1 TEMP2 TEMP3 DVDD/4 AVDD/4 LOWER MUX UPPER MUX
DPIO4 PGA AV = 1, 2, 4, 8 APIO1 DITHER ACCUMULATOR ALARM ADC FIFO AV = 0.5, 0.8192, 1.0 2.50V BANDGAP AV = 0.5, 0.8192, 1.0 APIO4 APIO APIO3 APIO2 12-BIT ADC REFADC
AIN1 AIN2
REFADC REFADJ REFDAC
SNO1 SNC1 SCM1 SPDT1
REFADC REFDAC AGND
REFDAC SNO2 SNC2 SCM2 IN1+ OA1 IN1OSW1 MAX1329 OUT1 REFDAC SPDT2 DACA FIFO
12-BIT DACA DSWA
OUTA
FBA
12-BIT DACB DSWB
OUTB
FBB
DGND
AGND
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
Functional Diagrams (continued)
DVDD CLKIO RST1 RST2 C1A C1B AVDD
MAX1329/MAX1330
CS SCLK DIN DOUT SERIAL I/O
INTERNAL CLOCK AND DIVIDER
VOLTAGE SUPERVISORS AND INTERRUPTS
CHARGE PUMP DPIO
DPIO1 DPIO2 DPIO3
AIN1 AIN2 OUTA FBA OUT1 IN1OUT2 IN2TEMP SENSOR TEMP1 TEMP2 TEMP3 DVDD/4 AVDD/4 LOWER MUX UPPER MUX
DPIO4 PGA AV = 1, 2, 4, 8 APIO1 DITHER ACCUMULATOR ALARM ADC FIFO AV = 0.5, 0.8192, 1.0 2.50V BANDGAP AV = 0.5, 0.8192, 1.0 APIO4 APIO APIO3 APIO2 12-BIT ADC REFADC
AIN1 AIN2
REFADC REFADJ REFDAC
SNO1 SNC1 SCM1 SPDT1
REFADC REFDAC AGND
REFDAC SNO2 SNC2 SCM2 IN1+ OA1 IN1OSW1 MAX1330 OUT1 SPDT2 DACA FIFO
12-BIT DACA DSWA
OUTA
FBA
OA2 OSW2
OUT2
IN2-
DGND
IN2+
AGND
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Typical Operating Circuit
1.8V TO 3.6V E1 10F 0.1F 1F 3.0V 33F 0.1F
DVDD AIN1
C1A
C1B
AVDD XIN 32.768kHz
VDD
AIN2 2N3904 1F REFADC REFADJ 0.01F 1F REFDAC
MAX1329
CLKIO XOUT HCLKIN C CS SCLK DIN DOUT OUTPUT SCK MOSI MISO
OUTA RF FBA WE SENSOR RE CE OUTB AGND DGND FBB
RST1 RST2
RESET INTERRUPT
DPIO1 DPIO2
INTERRUPT INTERRUPT
DGND
76
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor
Pin Configurations
TOP VIEW AIN2 SNO2 SCM2 SNC2 REFDAC FBA OUTA OUTB N.C. FBB TOP VIEW
REFDAC FBA OUTA OUT2 AIN2 SNO2 SCM2 SNC2 IN2+ IN2-
MAX1329/MAX1330
30 29 28 27 26 25 24 23 22 21 AIN1 REFADC REFADJ AGND AVDD C1B C1A DVDD DGND CLKIO 31 32 33 34 35 36 37 38 39 40 20 19 18 17 OUT1 IN1IN1+ SNC1 SCM1 SNO1 APIO4 APIO3 APIO2 APIO1 AIN1 REFADC REFADJ AGND AVDD C1B C1A DVDD DGND CLKIO 31 32 33 34 35 36 37 38 39 40
30 29 28 27 26 25 24 23 22 21 20 19 18 17 OUT1 IN1IN1+ SNC1 SCM1 SNO1 APIO4 APIO3 APIO2 APIO1
MAX1329
EXPOSED PAD-- CONNECT TO AGND
16 15 14 13 12 11
MAX1330
EXPOSED PAD-- CONNECT TO AGND
16 15 14 13 12 11
+
1 2 3 4 5 6 7 8 9 10 RST2 DPIO3 DPIO4 DOUT SCLK DPIO1 DPIO2 DIN CS RST1
+
1 2 3 4 5 6 7
DIN
8 9 10
CS RST1 RST2
THIN QFN
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 40 TQFN-EP PACKAGE CODE T4066-5 DOCUMENT NO. 21-0141
______________________________________________________________________________________
DPIO3 DPIO4 DOUT SCLK
DPIO1 DPIO2
THIN QFN
Package Information
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12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor MAX1329/MAX1330
Revision History
REVISION NUMBER 0 1 REVISION DATE 8/08 10/08 Initial release Corrected Absolute Maximum Ratings table DESCRIPTION PAGES CHANGED -- 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
78 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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